← Commit history

Publish 0.2.0

Ray ·3de8ba3117 ·1mo ago ·parent ae79c2f
3 files changed +24−7
README.md+14
@@ -38,6 +38,20 @@ SN74LVC1G04DCKR from UMW, in a SC-70-5. Pinout and pin descriptions extracted fr - Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5` - 3D model: SC-70-5 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74lvc1g04dckr.step`](sn74lvc1g04dckr.step) | 87 KB | You want the bare part, or you mark your own boards. |+| [`sn74lvc1g04dckr-etched.step`](sn74lvc1g04dckr-etched.step) | 2.4 MB | You want the part with `SN74LVC1G04DCKR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 601 faces against 102 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1
@@ -1,6 +1,6 @@ {   "slug": "sn74lvc1g04dckr",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "Unknown Inverters, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [
page.json+9−6
@@ -4,7 +4,7 @@   "slug": "sn74lvc1g04dckr",   "title": "SN74LVC1G04DCKR",   "brief": "UMW Inverters, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -41,7 +41,7 @@         "number": "2",         "name": "A",         "type": "input",-        "description": "Logic input to the inverter. CMOS-compatible thresholds scale with VCC (VIH \u2248 0.7\u00b7VCC, VIL \u2248 0.3\u00b7VCC at VCC = 3-5.5 V). Input leakage typically 0.1 \u00b5A, absolute max \u00b15.5 V regardless of VCC."+        "description": "Logic input to the inverter. CMOS-compatible thresholds scale with VCC (VIH ≈ 0.7·VCC, VIL ≈ 0.3·VCC at VCC = 3-5.5 V). Input leakage typically 0.1 µA, absolute max ±5.5 V regardless of VCC."       },       {         "number": "3",@@ -53,13 +53,13 @@         "number": "4",         "name": "Y",         "type": "output",-        "description": "Inverted logic output (Y = /A). Push-pull CMOS drive rated up to \u00b132 mA at VCC = 4.5 V (\u00b116 mA at 3 V, \u00b18 mA at 2.3 V, \u00b14 mA at 1.65 V). Swings rail-to-rail into a light load."+        "description": "Inverted logic output (Y = /A). Push-pull CMOS drive rated up to ±32 mA at VCC = 4.5 V (±16 mA at 3 V, ±8 mA at 2.3 V, ±4 mA at 1.65 V). Swings rail-to-rail into a light load."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply, 1.65 V to 5.5 V operating (6.5 V absolute max). Bypass with a local 0.1 \u00b5F ceramic to GND. Static ICC ~0.1 \u00b5A typical."+        "description": "Positive supply, 1.65 V to 5.5 V operating (6.5 V absolute max). Bypass with a local 0.1 µF ceramic to GND. Static ICC ~0.1 µA typical."       }     ],     "provenance": {@@ -133,6 +133,9 @@     "docs/hero.png",     "docs/sn74lvc1g04dckr-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"-  ]+    "viewers/footprint.html",+    "pads.json"+  ],+  "description": "Unknown Inverters, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "visibility": "public" }\ No newline at end of file