component
SN74LVC1G04DCKR
Public Made by Adomby adom
UMW Inverters, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (DIGIKEY_PN 4518-SN74LVC1G04DCKRTR-ND, LCSC_PN C2983744). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+28−6
page.json+7−4@@ -26,7 +26,10 @@ "model_3d_step": "sn74lvc1g04dckr.step", "lbr": "sn74lvc1g04dckr.lbr" },- "distributor_links": {},+ "distributor_links": {+ "digikey": "4518-SN74LVC1G04DCKRTR-ND",+ "lcsc": "C2983744"+ }, "pins": [ { "number": "1",@@ -38,7 +41,7 @@ "number": "2", "name": "A", "type": "input",- "description": "Logic input to the inverter. CMOS-compatible thresholds scale with VCC (VIH ≈ 0.7·VCC, VIL ≈ 0.3·VCC at VCC = 3-5.5 V). Input leakage typically 0.1 µA, absolute max ±5.5 V regardless of VCC."+ "description": "Logic input to the inverter. CMOS-compatible thresholds scale with VCC (VIH \u2248 0.7\u00b7VCC, VIL \u2248 0.3\u00b7VCC at VCC = 3-5.5 V). Input leakage typically 0.1 \u00b5A, absolute max \u00b15.5 V regardless of VCC." }, { "number": "3",@@ -50,13 +53,13 @@ "number": "4", "name": "Y", "type": "output",- "description": "Inverted logic output (Y = /A). Push-pull CMOS drive rated up to ±32 mA at VCC = 4.5 V (±16 mA at 3 V, ±8 mA at 2.3 V, ±4 mA at 1.65 V). Swings rail-to-rail into a light load."+ "description": "Inverted logic output (Y = /A). Push-pull CMOS drive rated up to \u00b132 mA at VCC = 4.5 V (\u00b116 mA at 3 V, \u00b18 mA at 2.3 V, \u00b14 mA at 1.65 V). Swings rail-to-rail into a light load." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply, 1.65 V to 5.5 V operating (6.5 V absolute max). Bypass with a local 0.1 µF ceramic to GND. Static ICC ~0.1 µA typical."+ "description": "Positive supply, 1.65 V to 5.5 V operating (6.5 V absolute max). Bypass with a local 0.1 \u00b5F ceramic to GND. Static ICC ~0.1 \u00b5A typical." } ], "provenance": {
sn74lvc1g04dckr.lbr+21−2@@ -59,6 +59,18 @@ <smd name="3" x="-0.8375" y="-0.6500" dx="1.0250" dy="0.3500" layer="1"/> <smd name="4" x="0.8375" y="-0.6500" dx="1.0250" dy="0.3500" layer="1"/> <smd name="5" x="0.8375" y="0.6500" dx="1.0250" dy="0.3500" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.1800" y="1.0900"/>+ <vertex x="-1.3200" y="1.2800"/>+ <vertex x="-1.0400" y="1.2800"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.3125" y="1.0000"/>+ <vertex x="0.6250" y="1.0000"/>+ <vertex x="0.6250" y="-1.0000"/>+ <vertex x="-0.6250" y="-1.0000"/>+ <vertex x="-0.6250" y="0.6875"/>+ </polygon> <wire x1="-0.7350" y1="1.1100" x2="0.7350" y2="1.1100" width="0.1200" layer="21"/> <wire x1="-0.7350" y1="1.0850" x2="-0.7350" y2="1.1100" width="0.1200" layer="21"/> <wire x1="-0.7350" y1="-1.1100" x2="-0.7350" y2="-1.0850" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.7350" y1="-1.1100" x2="-0.7350" y2="-1.1100" width="0.1200" layer="21"/> <text x="0" y="1.763" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-1.763" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.1800" y="1.0900"/><vertex x="-1.3200" y="1.2800"/><vertex x="-1.0400" y="1.2800"/></polygon></package>+</package> </packages> <symbols> <symbol name="SN74LVC1G04DCKR">@@ -100,7 +112,14 @@ <connect gate="G$1" pin="VCC" pad="5"/> <connect gate="G$1" pin="Y" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="SN74LVC1G04DCKR" constant="no"/>+ <attribute name="MANUFACTURER" value="UMW" constant="no"/>+ <attribute name="DIGIKEY_PN" value="4518-SN74LVC1G04DCKRTR-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C2983744" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>