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Set visibility: public

Ray ·fcda18c3bf ·1mo ago ·parent 7282905
1 file changed +7−4
page.json+7−4
@@ -38,7 +38,7 @@         "number": "2",         "name": "A",         "type": "input",-        "description": "Logic input to the inverter gate. Accepts input voltages up to 5.5 V regardless of VCC (down-translation). VIH/VIL thresholds scale with VCC (e.g. 0.7\u00b7VCC / 0.3\u00b7VCC at VCC = 4.5-5.5 V)."+        "description": "Logic input to the inverter gate. Accepts input voltages up to 5.5 V regardless of VCC (down-translation). VIH/VIL thresholds scale with VCC (e.g. 0.7·VCC / 0.3·VCC at VCC = 4.5-5.5 V)."       },       {         "number": "3",@@ -50,13 +50,13 @@         "number": "4",         "name": "Y",         "type": "output",-        "description": "Inverted logic output, Y = /A. CMOS push-pull drive of \u00b124 mA at VCC = 3 V (up to \u00b132 mA at 4.5 V, \u00b14 mA at 1.65 V)."+        "description": "Inverted logic output, Y = /A. CMOS push-pull drive of ±24 mA at VCC = 3 V (up to ±32 mA at 4.5 V, ±4 mA at 1.65 V)."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply, 1.65 V to 5.5 V operating (1.5 V minimum for data retention only). Typical quiescent current ICC \u2264 10 \u00b5A."+        "description": "Positive supply, 1.65 V to 5.5 V operating (1.5 V minimum for data retention only). Typical quiescent current ICC ≤ 10 µA."       }     ],     "provenance": {@@ -120,5 +120,8 @@     "docs/sn74lvc1g04dbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file