component
SN74LVC1G02DRLR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOT-553-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+41@@ -0,0 +1,41 @@+# SN74LVC1G02DRLR++**Texas Instruments** · Logic Gates · SOT-553-5++SN74LVC1G02DRLR from Texas Instruments, in a SOT-553-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Logic input accepting voltages from 0 to 5.5V with maximum input leakage current of ±5μA and high-impedance CMOS input structure. |+| 2 | B | input | Logic input accepting voltages from 0 to 5.5V with maximum input leakage current of ±5μA and high-impedance CMOS input structure. |+| 3 | GND | power_in | Ground reference connection; device return path capable of sinking maximum total current of 100mA including output pull-down and supply currents. |+| 4 | Y | output | NOR gate output (Y = A•B in positive logic) with push-pull CMOS balanced output capable of sourcing/sinking maximum ±24mA at 3.3V and output voltage range 0 to VCC. |+| 5 | VCC | power_out | Positive power supply terminal with recommended operating voltage range 1.65V to 5.5V and maximum quiescent supply current of 10μA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOT-553-5 |+| Category | Logic |+| Pins | 5 |++## CAD (KiCad official)++- Symbol: `SN74LVC1G02DRLR`+- Footprint: `Package_TO_SOT_SMD:SOT-553`+- 3D model: SOT-553-5 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc1g02drlr-etched.step` / `sn74lvc1g02drlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc1g02drlr.step` / `sn74lvc1g02drlr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc1g02.pdf) (49 pp, sha256 `38895735614b7fee`, retrieved 2026-09-27, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc1g02drlr-datasheet.pdf)
page.jsonadded+137@@ -0,0 +1,137 @@+{+ "slug": "sn74lvc1g02drlr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOT-553-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvc1g02drlr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc1g02drlr.kicad_sym",+ "sn74lvc1g02drlr.kicad_mod",+ "sn74lvc1g02drlr.glb",+ "sn74lvc1g02drlr.step",+ "sn74lvc1g02drlr.lbr",+ "docs/hero.png",+ "docs/sn74lvc1g02drlr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "SN74LVC1G02DRLR",+ "manufacturer": "Texas Instruments",+ "package": "SOT-553-5",+ "pin_count": 5,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc1g02.pdf",+ "parts": {+ "symbol": "sn74lvc1g02drlr.kicad_sym",+ "footprint": "sn74lvc1g02drlr.kicad_mod",+ "model_3d": "sn74lvc1g02drlr-etched.glb",+ "model_3d_plain": "sn74lvc1g02drlr.glb",+ "model_3d_step": "sn74lvc1g02drlr-etched.step",+ "model_3d_step_plain": "sn74lvc1g02drlr.step",+ "lbr": "sn74lvc1g02drlr.lbr"+ },+ "distributor_links": {+ "lcsc": "C194998",+ "digikey": "296-18318-2-ND",+ "mouser": "595-SN74LVC1G02DRLR"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T13:46:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-18318-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN74LVC1G02DRLR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Logic input accepting voltages from 0 to 5.5V with maximum input leakage current of ±5μA and high-impedance CMOS input structure."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Logic input accepting voltages from 0 to 5.5V with maximum input leakage current of ±5μA and high-impedance CMOS input structure."+ },+ {+ "number": "3",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference connection; device return path capable of sinking maximum total current of 100mA including output pull-down and supply currents."+ },+ {+ "number": "4",+ "name": "Y",+ "type": "output",+ "description": "NOR gate output (Y = A•B in positive logic) with push-pull CMOS balanced output capable of sourcing/sinking maximum ±24mA at 3.3V and output voltage range 0 to VCC."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_out",+ "description": "Positive power supply terminal with recommended operating voltage range 1.65V to 5.5V and maximum quiescent supply current of 10μA."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 49,+ "cost_usd": 0.2744,+ "at": "2026-09-27T13:46:27"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvc1g02.pdf",+ "pages": 49,+ "sha256": "38895735614b7fee",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 5,+ "described": 5,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}