SN74LV595APWR

@@ -0,0 +1,64 @@+# SN74LV595APWR++**Texas Instruments** · Shifting Register · TSSOP-16++SN74LV595APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | tri_state | Parallel output B from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 2 | QC | tri_state | Parallel output C from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 3 | QD | tri_state | Parallel output D from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 4 | QE | tri_state | Parallel output E from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 5 | QF | tri_state | Parallel output F from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 6 | QG | tri_state | Parallel output G from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 7 | QH | tri_state | Parallel output H from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 8 | GND | power_in | Ground reference (0 V). All signal voltages are referenced to this pin. |+| 9 | QH' | output | Serial data output from the shift register's last stage (QH of the shift register, before the storage register). Used to cascade multiple '595A devices; not 3-state. |+| 10 | SRCLR | input | Shift register direct clear input, active LOW. When LOW, asynchronously clears the 8-bit shift register. |+| 11 | SRCLK | input | Shift register clock input. Positive-edge triggered; on each rising edge the SER data is shifted into the 8-bit shift register. |+| 12 | RCLK | input | Storage register clock input. Positive-edge triggered; on each rising edge the shift register contents are latched into the 8-bit storage (D-type) register that drives QA..QH. |+| 13 | OE | input | Output enable, active LOW. When LOW the parallel outputs QA..QH are enabled; when HIGH the outputs go to high impedance (3-state). |+| 14 | SER | input | Serial data input to the 8-bit shift register. Sampled on the rising edge of SRCLK. |+| 15 | QA | tri_state | Parallel output A from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH. |+| 16 | VCC | power_in | Positive supply voltage, 2 V to 5.5 V (absolute maximum 7 V). Decouple locally with a 0.1 uF ceramic capacitor to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `SN74LV595APWRPW`+- `SN74LV595APWRPWR`+- `SN74LV595APWRD`+- `SN74LV595APWRDR`+- `SN74LV595APWRNS`+- `SN74LV595APWRNSR`+- `SN74LV595APWRRGY`+- `SN74LV595APWRRGYR`+- `SN74LV595APWRBQB`+- `SN74LV595APWRBQBR`++## CAD (KiCad official)++- Symbol: `SN74LV595APWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv595a.pdf) (37 pp, sha256 `191b0e955c531d56`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv595apwr-datasheet.pdf)

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