component
SN74LV595APWR
Public Made by Adomby adom
Texas Instruments Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74lv595apwr",+ "title": "SN74LV595APWR",+ "brief": "Texas Instruments Shifting Register, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Shifting Register, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74lv595apwr" ],+ "component": {+ "mpn": "SN74LV595APWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shifting Register",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lv595a.pdf",+ "parts": {+ "symbol": "sn74lv595apwr.kicad_sym",+ "footprint": "sn74lv595apwr.kicad_mod",+ "model_3d": "sn74lv595apwr.glb",+ "model_3d_step": "sn74lv595apwr.step",+ "lbr": "sn74lv595apwr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "QB",+ "type": "tri_state",+ "description": "Parallel output B from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "2",+ "name": "QC",+ "type": "tri_state",+ "description": "Parallel output C from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "3",+ "name": "QD",+ "type": "tri_state",+ "description": "Parallel output D from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "4",+ "name": "QE",+ "type": "tri_state",+ "description": "Parallel output E from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "5",+ "name": "QF",+ "type": "tri_state",+ "description": "Parallel output F from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "6",+ "name": "QG",+ "type": "tri_state",+ "description": "Parallel output G from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "7",+ "name": "QH",+ "type": "tri_state",+ "description": "Parallel output H from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). All signal voltages are referenced to this pin."+ },+ {+ "number": "9",+ "name": "QH'",+ "type": "output",+ "description": "Serial data output from the shift register's last stage (QH of the shift register, before the storage register). Used to cascade multiple '595A devices; not 3-state."+ },+ {+ "number": "10",+ "name": "SRCLR",+ "type": "input",+ "description": "Shift register direct clear input, active LOW. When LOW, asynchronously clears the 8-bit shift register."+ },+ {+ "number": "11",+ "name": "SRCLK",+ "type": "input",+ "description": "Shift register clock input. Positive-edge triggered; on each rising edge the SER data is shifted into the 8-bit shift register."+ },+ {+ "number": "12",+ "name": "RCLK",+ "type": "input",+ "description": "Storage register clock input. Positive-edge triggered; on each rising edge the shift register contents are latched into the 8-bit storage (D-type) register that drives QA..QH."+ },+ {+ "number": "13",+ "name": "OE",+ "type": "input",+ "description": "Output enable, active LOW. When LOW the parallel outputs QA..QH are enabled; when HIGH the outputs go to high impedance (3-state)."+ },+ {+ "number": "14",+ "name": "SER",+ "type": "input",+ "description": "Serial data input to the 8-bit shift register. Sampled on the rising edge of SRCLK."+ },+ {+ "number": "15",+ "name": "QA",+ "type": "tri_state",+ "description": "Parallel output A from the 8-bit storage register. 3-state CMOS output; disabled to high-impedance when OE is HIGH."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2 V to 5.5 V (absolute maximum 7 V). Decouple locally with a 0.1 uF ceramic capacitor to GND."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lv595a.pdf",+ "pages": 37,+ "sha256": "191b0e955c531d56",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "TSSOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74lv595apwr"+ ],+ "discovery_pitch": "SN74LV595APWR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/sn74lv595apwr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }