← Commit history

Initial commit: component/sn74lv4052apwr

Ray ·6c7ce10b92 ·1mo ago
2 files changed +97
README.mdadded+63
@@ -0,0 +1,63 @@+# SN74LV4052APWR++**Texas Instruments** · Analog Switches, Multiplexers · TSSOP-16++SN74LV4052APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 2Y0 | bidirectional | Port 2 channel 0 analog switch terminal. Signal path to 2-COM when INH=L and select code B,A=00. Analog signal range 0 to VCC. |+| 2 | 2Y2 | bidirectional | Port 2 channel 2 analog switch terminal. Signal path to 2-COM when INH=L and select code B,A=10. Analog signal range 0 to VCC. |+| 3 | 2-COM | bidirectional | Port 2 common (pole) terminal. Connects to one of 2Y0-2Y3 depending on the B,A select code when INH is low. |+| 4 | 2Y3 | bidirectional | Port 2 channel 3 analog switch terminal. Signal path to 2-COM when INH=L and select code B,A=11. |+| 5 | 2Y1 | bidirectional | Port 2 channel 1 analog switch terminal. Signal path to 2-COM when INH=L and select code B,A=01. |+| 6 | INH | input | Inhibit (enable-bar) input. When INH=H all switches are OFF (high impedance); when INH=L the switch selected by B,A is enabled. Logic-level input referenced to VCC. |+| 7 | GND | power_in | Device ground. Also sets the lower rail of the analog switch signal range (VIO min = 0V, i.e. GND). |+| 8 | GND | power_in | Device ground (second GND pin). Tie to the same ground plane as pin 7. |+| 9 | B | input | Logic input selector B (MSB of the 2-bit channel-select code B,A). Together with A selects one of the four Y channels for each pole. |+| 10 | A | input | Logic input selector A (LSB of the 2-bit channel-select code B,A). Together with B selects one of the four Y channels for each pole. |+| 11 | 1Y3 | bidirectional | Port 1 channel 3 analog switch terminal. Signal path to 1-COM when INH=L and select code B,A=11. |+| 12 | 1Y0 | bidirectional | Port 1 channel 0 analog switch terminal. Signal path to 1-COM when INH=L and select code B,A=00. |+| 13 | 1-COM | bidirectional | Port 1 common (pole) terminal. Connects to one of 1Y0-1Y3 depending on the B,A select code when INH is low. |+| 14 | 1Y1 | bidirectional | Port 1 channel 1 analog switch terminal. Signal path to 1-COM when INH=L and select code B,A=01. |+| 15 | 1Y2 | bidirectional | Port 1 channel 2 analog switch terminal. Signal path to 1-COM when INH=L and select code B,A=10. |+| 16 | VCC | power_in | Device power supply, 1.65V to 5.5V. Also sets the upper analog signal rail (VIO max = VCC). Bypass with 0.1 uF close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Interface |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `SN74LV4052APWR`+- `SN74LV4052APWRD`+- `SN74LV4052APWRDR`+- `SN74LV4052APWRRGY`+- `SN74LV4052APWRRGYR`+- `SN74LV4052APWRDYY`+- `SN74LV4052APWRDYYR`++## CAD (KiCad official)++- Symbol: `SN74LV4052APWR`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv4052a.pdf) (43 pp, sha256 `d6b3adfc74fd414e`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv4052apwr-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "sn74lv4052apwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Analog Switches, Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "interface",+    "sn74lv4052apwr"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74lv4052apwr.kicad_sym",+    "sn74lv4052apwr.kicad_mod",+    "sn74lv4052apwr.glb",+    "sn74lv4052apwr.step",+    "sn74lv4052apwr.lbr",+    "docs/hero.png",+    "docs/sn74lv4052apwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file