component
SN74LV273APWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+188−8@@ -1,13 +1,198 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74lv273apwr",+ "title": "SN74LV273APWR",+ "brief": "Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74lv273apwr" ],+ "component": {+ "mpn": "SN74LV273APWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lv273a.pdf",+ "parts": {+ "symbol": "sn74lv273apwr.kicad_sym",+ "footprint": "sn74lv273apwr.kicad_mod",+ "model_3d": "sn74lv273apwr.glb",+ "model_3d_step": "sn74lv273apwr.step",+ "lbr": "sn74lv273apwr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear input. Driving CLR low forces all eight Q outputs low independently of CLK."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "output",+ "description": "Flip-flop 1 Q output. Follows 1D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Flip-flop 1 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Flip-flop 2 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "output",+ "description": "Flip-flop 2 Q output. Follows 2D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "output",+ "description": "Flip-flop 3 Q output. Follows 3D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Flip-flop 3 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Flip-flop 4 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "output",+ "description": "Flip-flop 4 Q output. Follows 4D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground reference (0 V)."+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Common clock input for all eight flip-flops. Data on the D inputs is transferred to the Q outputs on the rising edge."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "output",+ "description": "Flip-flop 5 Q output. Follows 5D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Flip-flop 5 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Flip-flop 6 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "output",+ "description": "Flip-flop 6 Q output. Follows 6D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "output",+ "description": "Flip-flop 7 Q output. Follows 7D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Flip-flop 7 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Flip-flop 8 D data input. Sampled on the rising edge of CLK."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "output",+ "description": "Flip-flop 8 Q output. Follows 8D on the rising edge of CLK; forced low when CLR is low."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply input, 2 V to 5.5 V (absolute max 7 V)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lv273a.pdf",+ "pages": 45,+ "sha256": "d29b4a0410bdb60f",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "TSSOP-20",+ "Category": "Logic",+ "Pins": "20"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74lv273apwr"+ ],+ "discovery_pitch": "SN74LV273APWR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +210,5 @@ "docs/sn74lv273apwr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }