SN74LV273APWR

@@ -0,0 +1,67 @@+# SN74LV273APWR++**Texas Instruments** · Flip Flops · TSSOP-20++SN74LV273APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Active-low asynchronous clear input. Driving CLR low forces all eight Q outputs low independently of CLK. |+| 2 | 1Q | output | Flip-flop 1 Q output. Follows 1D on the rising edge of CLK; forced low when CLR is low. |+| 3 | 1D | input | Flip-flop 1 D data input. Sampled on the rising edge of CLK. |+| 4 | 2D | input | Flip-flop 2 D data input. Sampled on the rising edge of CLK. |+| 5 | 2Q | output | Flip-flop 2 Q output. Follows 2D on the rising edge of CLK; forced low when CLR is low. |+| 6 | 3Q | output | Flip-flop 3 Q output. Follows 3D on the rising edge of CLK; forced low when CLR is low. |+| 7 | 3D | input | Flip-flop 3 D data input. Sampled on the rising edge of CLK. |+| 8 | 4D | input | Flip-flop 4 D data input. Sampled on the rising edge of CLK. |+| 9 | 4Q | output | Flip-flop 4 Q output. Follows 4D on the rising edge of CLK; forced low when CLR is low. |+| 10 | GND | power_in | Device ground reference (0 V). |+| 11 | CLK | input | Common clock input for all eight flip-flops. Data on the D inputs is transferred to the Q outputs on the rising edge. |+| 12 | 5Q | output | Flip-flop 5 Q output. Follows 5D on the rising edge of CLK; forced low when CLR is low. |+| 13 | 5D | input | Flip-flop 5 D data input. Sampled on the rising edge of CLK. |+| 14 | 6D | input | Flip-flop 6 D data input. Sampled on the rising edge of CLK. |+| 15 | 6Q | output | Flip-flop 6 Q output. Follows 6D on the rising edge of CLK; forced low when CLR is low. |+| 16 | 7Q | output | Flip-flop 7 Q output. Follows 7D on the rising edge of CLK; forced low when CLR is low. |+| 17 | 7D | input | Flip-flop 7 D data input. Sampled on the rising edge of CLK. |+| 18 | 8D | input | Flip-flop 8 D data input. Sampled on the rising edge of CLK. |+| 19 | 8Q | output | Flip-flop 8 Q output. Follows 8D on the rising edge of CLK; forced low when CLR is low. |+| 20 | VCC | power_in | Positive supply input, 2 V to 5.5 V (absolute max 7 V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## Ordering variants++- `SN74LV273APWRPW`+- `SN74LV273APWRPWR`+- `SN74LV273APWRDB`+- `SN74LV273APWRDGV`+- `SN74LV273APWRDW`+- `SN74LV273APWRNS`+- `SN74LV273APWRRGY`+- `SN74LV273APWRRKS`+- `SN74LV273APWRDGS`++## CAD (KiCad official)++- Symbol: `SN74LV273APWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv273a.pdf) (45 pp, sha256 `d29b4a0410bdb60f`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv273apwr-datasheet.pdf)

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