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SN74LV132ADR
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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74LV132ADR++**Texas Instruments** · Logic Gates · SOIC-14++SN74LV132ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Data input 1A of NAND gate 1; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 2 | 1B | input | Data input 1B of NAND gate 1; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 3 | 1Y | output | Output 1Y of NAND gate 1; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |+| 4 | 2A | input | Data input 2A of NAND gate 2; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 5 | 2B | input | Data input 2B of NAND gate 2; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 6 | 2Y | output | Output 2Y of NAND gate 2; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |+| 7 | GND | power_in | Ground reference for the device. |+| 8 | 3Y | output | Output 3Y of NAND gate 3; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |+| 9 | 3A | input | Data input 3A of NAND gate 3; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 10 | 3B | input | Data input 3B of NAND gate 3; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 11 | 4Y | output | Output 4Y of NAND gate 4; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |+| 12 | 4A | input | Data input 4A of NAND gate 4; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 13 | 4B | input | Data input 4B of NAND gate 4; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |+| 14 | VCC | power_in | Supply voltage, recommended operating range 2 V to 5.5 V; bypass with a 0.1 µF capacitor placed as close to the pin as possible. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LV132ADR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lv132adr-etched.step` / `sn74lv132adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv132adr.step` / `sn74lv132adr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv132a.pdf) (28 pp, sha256 `eb436a12dc7197d7`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv132adr-datasheet.pdf)
page.jsonadded+235@@ -0,0 +1,235 @@+{+ "slug": "sn74lv132adr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lv132adr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lv132adr.kicad_sym",+ "sn74lv132adr.kicad_mod",+ "sn74lv132adr.glb",+ "sn74lv132adr.step",+ "sn74lv132adr.lbr",+ "docs/hero.png",+ "docs/sn74lv132adr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lv132adr-hero.glb",+ "sn74lv132adr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LV132ADR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lv132a.pdf",+ "parts": {+ "symbol": "sn74lv132adr.kicad_sym",+ "footprint": "sn74lv132adr.kicad_mod",+ "model_3d": "sn74lv132adr-hero.glb",+ "model_3d_plain": "sn74lv132adr.glb",+ "model_3d_step": "sn74lv132adr-etched.step",+ "model_3d_step_plain": "sn74lv132adr.step",+ "lbr": "sn74lv132adr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2859847",+ "digikey": "296-1675-2-ND",+ "mouser": "595-SN74LV132ADR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:45:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-1675-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN74LV132ADR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Data input 1A of NAND gate 1; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Data input 1B of NAND gate 1; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Output 1Y of NAND gate 1; load current should not exceed 25 mA per output and the output should not be pulled above VCC."+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Data input 2A of NAND gate 2; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Data input 2B of NAND gate 2; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Output 2Y of NAND gate 2; load current should not exceed 25 mA per output and the output should not be pulled above VCC."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Output 3Y of NAND gate 3; load current should not exceed 25 mA per output and the output should not be pulled above VCC."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Data input 3A of NAND gate 3; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Data input 3B of NAND gate 3; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Output 4Y of NAND gate 4; load current should not exceed 25 mA per output and the output should not be pulled above VCC."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Data input 4A of NAND gate 4; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Data input 4B of NAND gate 4; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended operating range 2 V to 5.5 V; bypass with a 0.1 µF capacitor placed as close to the pin as possible."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin table is printed once for the D, DB, DGV, NS and PW packages together. The D (SOIC-14) pinou; The datasheet's Pin Functions table gives only a name and I/O direction for each pin. The descriptio"+ ],+ "pages_sent": 28,+ "cost_usd": 0.0998,+ "at": "2026-10-08T18:45:08"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lv132a.pdf",+ "pages": 28,+ "sha256": "eb436a12dc7197d7",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lv132adr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lv132adr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "216ba290f01c27fc7e252e4699738a622fbcb387c8e129e89b12d420acc79484",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}