component
SN74LV08ADBR
Public Made by Adomby adom
Texas Instruments Logic Gates, SSOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+51@@ -0,0 +1,51 @@+# SN74LV08ADBR++**Texas Instruments** · Logic Gates · SSOP-14-208mil++SN74LV08ADBR from Texas Instruments, in a SSOP-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | First AND gate input A; accepts logic levels from 0V to VCC |+| 2 | 1B | input | First AND gate input B; accepts logic levels from 0V to VCC |+| 3 | 1Y | output | First AND gate output; Y = 1A AND 1B, maximum sink/source current ±25 mA |+| 4 | 2A | input | Second AND gate input A; accepts logic levels from 0V to VCC |+| 5 | 2B | input | Second AND gate input B; accepts logic levels from 0V to VCC |+| 6 | 2Y | output | Second AND gate output; Y = 2A AND 2B, maximum sink/source current ±25 mA |+| 7 | GND | power_in | Ground reference, 0V |+| 8 | 3Y | output | Third AND gate output; Y = 3A AND 3B, maximum sink/source current ±25 mA |+| 9 | 3A | input | Third AND gate input A; accepts logic levels from 0V to VCC |+| 10 | 3B | input | Third AND gate input B; accepts logic levels from 0V to VCC |+| 11 | 4Y | output | Fourth AND gate output; Y = 4A AND 4B, maximum sink/source current ±25 mA |+| 12 | 4A | input | Fourth AND gate input A; accepts logic levels from 0V to VCC |+| 13 | 4B | input | Fourth AND gate input B; accepts logic levels from 0V to VCC |+| 14 | VCC | power_in | Positive power supply, 2V to 5.5V nominal operating range |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SSOP-14-208mil |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LV08ADBR`+- Footprint: `Package_SO:SSOP-14_5.3x6.2mm_P0.65mm`+- 3D model: SSOP-14-208mil (KiCad packages3D, STEP)+- 3D model files: `sn74lv08adbr-etched.step` / `sn74lv08adbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv08adbr.step` / `sn74lv08adbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lv08a) (30 pp, sha256 `9387bd563ce446e9`, retrieved 2026-09-27, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv08adbr-datasheet.pdf)
page.jsonadded+192@@ -0,0 +1,192 @@+{+ "slug": "sn74lv08adbr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SSOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lv08adbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lv08adbr.kicad_sym",+ "sn74lv08adbr.kicad_mod",+ "sn74lv08adbr.glb",+ "sn74lv08adbr.step",+ "sn74lv08adbr.lbr",+ "docs/hero.png",+ "docs/sn74lv08adbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "SN74LV08ADBR",+ "manufacturer": "Texas Instruments",+ "package": "SSOP-14-208mil",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lv08a",+ "parts": {+ "symbol": "sn74lv08adbr.kicad_sym",+ "footprint": "sn74lv08adbr.kicad_mod",+ "model_3d": "sn74lv08adbr-etched.glb",+ "model_3d_plain": "sn74lv08adbr.glb",+ "model_3d_step": "sn74lv08adbr-etched.step",+ "model_3d_step_plain": "sn74lv08adbr.step",+ "lbr": "sn74lv08adbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2872819",+ "digikey": "296-3768-2-ND",+ "mouser": "595-SN74LV08ADBR"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T10:53:32Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-3768-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74LV08ADBR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "First AND gate input A; accepts logic levels from 0V to VCC"+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "First AND gate input B; accepts logic levels from 0V to VCC"+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "First AND gate output; Y = 1A AND 1B, maximum sink/source current ±25 mA"+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Second AND gate input A; accepts logic levels from 0V to VCC"+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Second AND gate input B; accepts logic levels from 0V to VCC"+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Second AND gate output; Y = 2A AND 2B, maximum sink/source current ±25 mA"+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, 0V"+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Third AND gate output; Y = 3A AND 3B, maximum sink/source current ±25 mA"+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Third AND gate input A; accepts logic levels from 0V to VCC"+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Third AND gate input B; accepts logic levels from 0V to VCC"+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Fourth AND gate output; Y = 4A AND 4B, maximum sink/source current ±25 mA"+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Fourth AND gate input A; accepts logic levels from 0V to VCC"+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Fourth AND gate input B; accepts logic levels from 0V to VCC"+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive power supply, 2V to 5.5V nominal operating range"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 30,+ "cost_usd": 0.2156,+ "at": "2026-09-27T10:53:14"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lv08a",+ "pages": 30,+ "sha256": "9387bd563ce446e9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}