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SN74LV00APWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74LV00APWR++**Texas Instruments** · Logic Gates · TSSOP-14++SN74LV00APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input to the first 2-input NAND gate; rated for 0 to 5.5 V. |+| 2 | 1B | input | Input to the first 2-input NAND gate; rated for 0 to 5.5 V. |+| 3 | 1Y | output | Output of the first 2-input NAND gate; rated for 0 to VCC V. |+| 4 | 2A | input | Input to the second 2-input NAND gate; rated for 0 to 5.5 V. |+| 5 | 2B | input | Input to the second 2-input NAND gate; rated for 0 to 5.5 V. |+| 6 | 2Y | output | Output of the second 2-input NAND gate; rated for 0 to VCC V. |+| 7 | GND | power_in | Ground connection; return path for supply current. |+| 8 | 3Y | output | Output of the third 2-input NAND gate; rated for 0 to VCC V. |+| 9 | 3A | input | Input to the third 2-input NAND gate; rated for 0 to 5.5 V. |+| 10 | 3B | input | Input to the third 2-input NAND gate; rated for 0 to 5.5 V. |+| 11 | 4Y | output | Output of the fourth 2-input NAND gate; rated for 0 to VCC V. |+| 12 | 4A | input | Input to the fourth 2-input NAND gate; rated for 0 to 5.5 V. |+| 13 | 4B | input | Input to the fourth 2-input NAND gate; rated for 0 to 5.5 V. |+| 14 | VCC | power_in | Power supply voltage; rated for 2 V to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LV00APWR`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lv00apwr-etched.step` / `sn74lv00apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv00apwr.step` / `sn74lv00apwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv00a.pdf) (29 pp, sha256 `2f428ff83532785d`, retrieved 2026-10-05, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv00apwr-datasheet.pdf)
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