SN74LS165ADR

@@ -0,0 +1,62 @@+# SN74LS165ADR++**Texas Instruments** · Shifting Register · SOIC-16++SN74LS165ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SH/LD | input | Shift/Load control. Low = parallel-load data at A-H into the register (asynchronous, overrides clock). High = enable serial shifting on CLK/CLK INH. Diode-clamped TTL input, R_eq ~13 kΩ nom. |+| 2 | CLK | input | Clock input. On the rising edge (with CLK INH low and SH/LD high), data shifts from QA toward QH. CLK and CLK INH are combined in a two-input positive-NOR gate, so either may serve as clock or inhibit. |+| 3 | E | input | Parallel data input for bit E of the 8-bit word. Loaded into the corresponding stage when SH/LD is low. TTL input, R_eq ~24 kΩ nom. |+| 4 | F | input | Parallel data input for bit F of the 8-bit word. Loaded into the corresponding stage when SH/LD is low. |+| 5 | G | input | Parallel data input for bit G of the 8-bit word. Loaded into the corresponding stage when SH/LD is low. |+| 6 | H | input | Parallel data input for bit H (last stage) of the 8-bit word. Loaded into the QH stage when SH/LD is low; also drives the QH/QH-bar outputs directly after load. |+| 7 | QH_N | output | Complementary serial output (inverted QH). Provides the inverse of the eighth-stage register bit. Totem-pole TTL output, IOH = -800 μA, IOL = 16 mA, V_OL ≤ 0.4 V. |+| 8 | GND | power_in | Ground / 0 V reference for the device. |+| 9 | QH | output | Serial data output from the eighth register stage. During serial shift this bit is presented at QH; use as the serial-out for cascading multiple '165A devices. Totem-pole TTL output. |+| 10 | SER | input | Serial data input. Data at SER is shifted into the QA stage on each rising clock edge when SH/LD is high and CLK INH is low. Used to cascade '165A devices (connect prior stage's QH to next stage's SER). |+| 11 | A | input | Parallel data input for bit A (first stage) of the 8-bit word. Loaded into QA when SH/LD is low. |+| 12 | B | input | Parallel data input for bit B of the 8-bit word. Loaded when SH/LD is low. |+| 13 | C | input | Parallel data input for bit C of the 8-bit word. Loaded when SH/LD is low. |+| 14 | D | input | Parallel data input for bit D of the 8-bit word. Loaded when SH/LD is low. |+| 15 | CLK INH | input | Clock inhibit. When high, blocks the CLK input (positive-NOR gating). Should be transitioned high only while CLK is high to avoid producing spurious clock edges. |+| 16 | VCC | power_in | Positive supply, 4.75 V to 5.25 V (SN74LS165A). Typical ICC ≈ 42 mA (max 63 mA); typical power dissipation 90 mW. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `SN74LS165ADRSN74LS165AD`+- `SN74LS165ADR`+- `SN74LS165ADRSN74LS165AN`+- `SN74LS165ADRSN74LS165ANSR`+- `SN74LS165ADRSN54LS165AJ`+- `SN74LS165ADRSNJ54LS165AJ`+- `SN74LS165ADRSNJ54LS165AW`+- `SN74LS165ADRSNJ54LS165AFK`++## CAD (KiCad official)++- Symbol: `SN74LS165ADR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ls165a.pdf) (25 pp, sha256 `1985012cf301bde1`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ls165adr-datasheet.pdf)

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