SN74LS164DR

@@ -0,0 +1,58 @@+# SN74LS164DR++**Texas Instruments** · Shifting Register · SOIC-14++SN74LS164DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Gated serial data input A. ANDed internally with serial input B to drive the first flip-flop's D input; either input held low inhibits new-data entry and forces the first stage low at the next clock edge. Diode-clamped LSTTL input, VIH >= 2 V, VIL <= 0.8 V. |+| 2 | B | input | Gated serial data input B. ANDed internally with serial input A; a high level here enables input A to determine the next state of the first flip-flop. Diode-clamped LSTTL input. |+| 3 | QA | output | Parallel output of shift-register stage A (first stage). Totem-pole LSTTL output, VOH >= 2.7 V @ IOH = -0.4 mA, VOL <= 0.5 V @ IOL = 8 mA. |+| 4 | QB | output | Parallel output of shift-register stage B. Totem-pole LSTTL output. |+| 5 | QC | output | Parallel output of shift-register stage C. Totem-pole LSTTL output. |+| 6 | QD | output | Parallel output of shift-register stage D. Totem-pole LSTTL output. |+| 7 | GND | power_in | Ground / 0 V reference for the device. |+| 8 | CLK | input | Clock input. Data at the serial inputs is shifted one stage on the low-to-high transition; clock frequency 0-25 MHz (36 MHz typical). Minimum pulse width tw = 20 ns; setup 15 ns, hold 5 ns. |+| 9 | CLR | input | Active-low asynchronous clear. Driving CLR low forces all Q outputs low independent of CLK; must be held high (with tsu(clear inactive) >= 20 ns before next clock edge) for normal shift operation. |+| 10 | QE | output | Parallel output of shift-register stage E. Totem-pole LSTTL output. |+| 11 | QF | output | Parallel output of shift-register stage F. Totem-pole LSTTL output. |+| 12 | QG | output | Parallel output of shift-register stage G. Totem-pole LSTTL output. |+| 13 | QH | output | Parallel output of shift-register stage H (last stage). Also functions as the serial output when cascading devices. Totem-pole LSTTL output. |+| 14 | VCC | power_in | Positive supply, 4.75 V to 5.25 V (5 V nominal) for SN74LS164. Recommended bypass with 0.1 uF to GND close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `SN74LS164DRD`+- `SN74LS164DRDR`+- `SN74LS164DRN`+- `SN74LS164DRJ`+- `SN74LS164DRW`+- `SN74LS164DRFK`++## CAD (KiCad official)++- Symbol: `SN74LS164DR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ls164.pdf) (25 pp, sha256 `a1ac7a9fe0ab2158`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ls164dr-datasheet.pdf)

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