component
SN74HC74PWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+198−8@@ -1,13 +1,208 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc74pwr",+ "title": "SN74HC74PWR",+ "brief": "Texas Instruments Flip Flops, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Flip Flops, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74hc74pwr" ],+ "component": {+ "mpn": "SN74HC74PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc74.pdf",+ "parts": {+ "symbol": "sn74hc74pwr.kicad_sym",+ "footprint": "sn74hc74pwr.kicad_mod",+ "model_3d": "sn74hc74pwr.glb",+ "model_3d_step": "sn74hc74pwr.step",+ "lbr": "sn74hc74pwr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "1CLR",+ "type": "input",+ "description": "Channel 1 asynchronous clear input, active low. Drives the Q output low (Q-bar high) independent of clock when asserted. CMOS input; tie high to VCC through a pull-up if unused."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Channel 1 data input. Value sampled on the rising edge of 1CLK and transferred to 1Q. Standard high-impedance CMOS input."+ },+ {+ "number": "3",+ "name": "1CLK",+ "type": "input",+ "description": "Channel 1 positive-edge-triggered clock input. Rising edge latches 1D into the flip-flop. Max clock frequency 36 MHz at VCC=6 V."+ },+ {+ "number": "4",+ "name": "1PRE",+ "type": "input",+ "description": "Channel 1 asynchronous preset input, active low. Forces the Q output high (Q-bar low) independent of clock when asserted. Tie high if unused."+ },+ {+ "number": "5",+ "name": "1Q",+ "type": "output",+ "description": "Channel 1 flip-flop output (Q). Push-pull CMOS output driven from the latched value of 1D."+ },+ {+ "number": "6",+ "name": "1Q_N",+ "type": "output",+ "description": "Channel 1 inverted flip-flop output (Q-bar). Push-pull CMOS output that is the logical complement of 1Q."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device (0 V)."+ },+ {+ "number": "8",+ "name": "2Q_N",+ "type": "output",+ "description": "Channel 2 inverted flip-flop output (Q-bar). Push-pull CMOS output that is the logical complement of 2Q."+ },+ {+ "number": "9",+ "name": "2Q",+ "type": "output",+ "description": "Channel 2 flip-flop output (Q). Push-pull CMOS output driven from the latched value of 2D."+ },+ {+ "number": "10",+ "name": "2PRE",+ "type": "input",+ "description": "Channel 2 asynchronous preset input, active low. Forces the Q output high (Q-bar low) independent of clock when asserted. Tie high if unused."+ },+ {+ "number": "11",+ "name": "2CLK",+ "type": "input",+ "description": "Channel 2 positive-edge-triggered clock input. Rising edge latches 2D into the flip-flop. Max clock frequency 36 MHz at VCC=6 V."+ },+ {+ "number": "12",+ "name": "2D",+ "type": "input",+ "description": "Channel 2 data input. Value sampled on the rising edge of 2CLK and transferred to 2Q. Standard high-impedance CMOS input."+ },+ {+ "number": "13",+ "name": "2CLR",+ "type": "input",+ "description": "Channel 2 asynchronous clear input, active low. Drives the Q output low (Q-bar high) independent of clock when asserted. Tie high if unused."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2 V to 6 V (absolute max 7 V). Bypass locally with a 0.1 \u00b5F ceramic capacitor to GND."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74hc74.pdf",+ "pages": 41,+ "sha256": "a60d59528e97fe91",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "TSSOP-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "variants": [+ {+ "mpn": "SN74HC74PWR",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRD",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRDR",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRDB",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRDBR",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRN",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRNS",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRNSR",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRJ",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRW",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74PWRFK",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc74pwr"+ ],+ "discovery_pitch": "SN74HC74PWR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +220,5 @@ "docs/sn74hc74pwr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }