SN74HC74PWR

@@ -0,0 +1,65 @@+# SN74HC74PWR++**Texas Instruments** · Flip Flops · TSSOP-14++SN74HC74PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLR | input | Channel 1 asynchronous clear input, active low. Drives the Q output low (Q-bar high) independent of clock when asserted. CMOS input; tie high to VCC through a pull-up if unused. |+| 2 | 1D | input | Channel 1 data input. Value sampled on the rising edge of 1CLK and transferred to 1Q. Standard high-impedance CMOS input. |+| 3 | 1CLK | input | Channel 1 positive-edge-triggered clock input. Rising edge latches 1D into the flip-flop. Max clock frequency 36 MHz at VCC=6 V. |+| 4 | 1PRE | input | Channel 1 asynchronous preset input, active low. Forces the Q output high (Q-bar low) independent of clock when asserted. Tie high if unused. |+| 5 | 1Q | output | Channel 1 flip-flop output (Q). Push-pull CMOS output driven from the latched value of 1D. |+| 6 | 1Q_N | output | Channel 1 inverted flip-flop output (Q-bar). Push-pull CMOS output that is the logical complement of 1Q. |+| 7 | GND | power_in | Ground reference for the device (0 V). |+| 8 | 2Q_N | output | Channel 2 inverted flip-flop output (Q-bar). Push-pull CMOS output that is the logical complement of 2Q. |+| 9 | 2Q | output | Channel 2 flip-flop output (Q). Push-pull CMOS output driven from the latched value of 2D. |+| 10 | 2PRE | input | Channel 2 asynchronous preset input, active low. Forces the Q output high (Q-bar low) independent of clock when asserted. Tie high if unused. |+| 11 | 2CLK | input | Channel 2 positive-edge-triggered clock input. Rising edge latches 2D into the flip-flop. Max clock frequency 36 MHz at VCC=6 V. |+| 12 | 2D | input | Channel 2 data input. Value sampled on the rising edge of 2CLK and transferred to 2Q. Standard high-impedance CMOS input. |+| 13 | 2CLR | input | Channel 2 asynchronous clear input, active low. Drives the Q output low (Q-bar high) independent of clock when asserted. Tie high if unused. |+| 14 | VCC | power_in | Positive supply voltage, 2 V to 6 V (absolute max 7 V). Bypass locally with a 0.1 µF ceramic capacitor to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++Same part, different packaging or reel option.++- `SN74HC74PWR`+- `SN74HC74PWRD`+- `SN74HC74PWRDR`+- `SN74HC74PWRDB`+- `SN74HC74PWRDBR`+- `SN74HC74PWRN`+- `SN74HC74PWRNS`+- `SN74HC74PWRNSR`+- `SN74HC74PWRJ`+- `SN74HC74PWRW`+- `SN74HC74PWRFK`++## CAD (KiCad official)++- Symbol: `SN74HC74PWR`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74hc74.pdf) (41 pp, sha256 `a60d59528e97fe91`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hc74pwr-datasheet.pdf)

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