SN74HC74

@@ -0,0 +1,58 @@+# SN74HC74++**Texas Instruments** · Dual D flip-flop · SOIC-14++Two independent D-type positive-edge-triggered flip-flops in high-speed CMOS, in a SOIC-14 package. On each rising clock edge Q takes the value on D; asynchronous active-low PRE (preset) and CLR (clear) override the clock to force Q high or low. Complementary Q and Q outputs are provided. The building block for registers, dividers, synchronizers, and simple state machines. Runs 2-6 V.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLR | input | Channel 1 asynchronous clear input, active low. Driving low forces 1Q low and 1Q̄ high regardless of CLK/D. VIL ≤ 1.35 V @ VCC=4.5 V; input clamp current ±20 mA max. |+| 2 | 1D | input | Channel 1 data input; sampled on the rising edge of 1CLK. Setup time 20 ns typ @ VCC=4.5 V, hold time 0 ns. |+| 3 | 1CLK | input | Channel 1 positive-edge-triggered clock input. Maximum clock frequency 31 MHz @ VCC=4.5 V, 36 MHz @ VCC=6 V. |+| 4 | 1PRE | input | Channel 1 asynchronous preset input, active low. Driving low forces 1Q high and 1Q̄ low regardless of CLK/D. Minimum pulse width 20 ns @ VCC=4.5 V. |+| 5 | 1Q | output | Channel 1 flip-flop output. Follows 1D at the rising edge of 1CLK. VOH ≥ 3.98 V @ IOH=-4 mA, VCC=4.5 V; propagation delay 20 ns typ from CLK. |+| 6 | 1Q̄ | output | Channel 1 inverted flip-flop output, complement of 1Q. |+| 7 | GND | power_in | Device ground reference (0 V). |+| 8 | 2Q̄ | output | Channel 2 inverted flip-flop output, complement of 2Q. |+| 9 | 2Q | output | Channel 2 flip-flop output. Follows 2D at the rising edge of 2CLK. |+| 10 | 2PRE | input | Channel 2 asynchronous preset input, active low. Driving low forces 2Q high and 2Q̄ low regardless of CLK/D. |+| 11 | 2CLK | input | Channel 2 positive-edge-triggered clock input. |+| 12 | 2D | input | Channel 2 data input; sampled on the rising edge of 2CLK. |+| 13 | 2CLR | input | Channel 2 asynchronous clear input, active low. Driving low forces 2Q low and 2Q̄ high regardless of CLK/D. |+| 14 | VCC | power_in | Positive supply. Operating range 2 V to 6 V (nom 5 V); absolute max 7 V. ICC ≤ 40 µA over temperature. |++## Key specifications++| Parameter | Value |+|---|---|+| Type | Dual D-type flip-flop |+| Trigger | Positive (rising) clock edge |+| Async controls | PRE + CLR (active-low) |+| Outputs | Q + Q (complementary) |+| Logic family | HC (high-speed CMOS) |+| Supply voltage | 2-6 V |+| Package | SOIC-14 |+| Body (L×W×H) | 8.65 × 3.9 × 1.75 mm |++## Ordering variants++- `SN74HC74D (SOIC-14, tube)`+- `SN74HC74DR (SOIC-14, tape & reel)`++## CAD (KiCad official)++- Symbol: `74xx:74HC74`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74hc74.pdf) (41 pp, sha256 `a60d59528e97fe91`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude) — every pin and dimension is cited to a datasheet page; refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hc74-datasheet.pdf)

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