component
SN74HC74
Public Made by Adomby adom
TI dual D-type positive-edge flip-flop, SOIC-14. Async preset/clear, HC CMOS, 2-6 V. Datasheet-verified.
← Commit history
sn74hc74: backfill missing artifacts (etch, variants)
3 files changed
+22873−10
diff truncated
README.md+2@@ -38,6 +38,8 @@ Two independent D-type positive-edge-triggered flip-flops in high-speed CMOS, in ## Ordering variants +Same part, different packaging or reel option.+ - `SN74HC74D (SOIC-14, tube)` - `SN74HC74DR (SOIC-14, tape & reel)`
page.json+21−10@@ -35,7 +35,7 @@ "number": "1", "name": "1CLR", "type": "input",- "description": "Channel 1 asynchronous clear input, active low. Driving low forces 1Q low and 1Q\u0304 high regardless of CLK/D. VIL \u2264 1.35 V @ VCC=4.5 V; input clamp current \u00b120 mA max."+ "description": "Channel 1 asynchronous clear input, active low. Driving low forces 1Q low and 1Q̄ high regardless of CLK/D. VIL ≤ 1.35 V @ VCC=4.5 V; input clamp current ±20 mA max." }, { "number": "2",@@ -53,17 +53,17 @@ "number": "4", "name": "1PRE", "type": "input",- "description": "Channel 1 asynchronous preset input, active low. Driving low forces 1Q high and 1Q\u0304 low regardless of CLK/D. Minimum pulse width 20 ns @ VCC=4.5 V."+ "description": "Channel 1 asynchronous preset input, active low. Driving low forces 1Q high and 1Q̄ low regardless of CLK/D. Minimum pulse width 20 ns @ VCC=4.5 V." }, { "number": "5", "name": "1Q", "type": "output",- "description": "Channel 1 flip-flop output. Follows 1D at the rising edge of 1CLK. VOH \u2265 3.98 V @ IOH=-4 mA, VCC=4.5 V; propagation delay 20 ns typ from CLK."+ "description": "Channel 1 flip-flop output. Follows 1D at the rising edge of 1CLK. VOH ≥ 3.98 V @ IOH=-4 mA, VCC=4.5 V; propagation delay 20 ns typ from CLK." }, { "number": "6",- "name": "1Q\u0304",+ "name": "1Q̄", "type": "output", "description": "Channel 1 inverted flip-flop output, complement of 1Q." },@@ -75,7 +75,7 @@ }, { "number": "8",- "name": "2Q\u0304",+ "name": "2Q̄", "type": "output", "description": "Channel 2 inverted flip-flop output, complement of 2Q." },@@ -89,7 +89,7 @@ "number": "10", "name": "2PRE", "type": "input",- "description": "Channel 2 asynchronous preset input, active low. Driving low forces 2Q high and 2Q\u0304 low regardless of CLK/D."+ "description": "Channel 2 asynchronous preset input, active low. Driving low forces 2Q high and 2Q̄ low regardless of CLK/D." }, { "number": "11",@@ -107,13 +107,13 @@ "number": "13", "name": "2CLR", "type": "input",- "description": "Channel 2 asynchronous clear input, active low. Driving low forces 2Q low and 2Q\u0304 high regardless of CLK/D."+ "description": "Channel 2 asynchronous clear input, active low. Driving low forces 2Q low and 2Q̄ high regardless of CLK/D." }, { "number": "14", "name": "VCC", "type": "power_in",- "description": "Positive supply. Operating range 2 V to 6 V (nom 5 V); absolute max 7 V. ICC \u2264 40 \u00b5A over temperature."+ "description": "Positive supply. Operating range 2 V to 6 V (nom 5 V); absolute max 7 V. ICC ≤ 40 µA over temperature." } ], "provenance": {@@ -146,7 +146,7 @@ "Logic family": "HC (high-speed CMOS)", "Supply voltage": "2-6 V", "Package": "SOIC-14",- "Body (L\u00d7W\u00d7H)": "8.65 \u00d7 3.9 \u00d7 1.75 mm"+ "Body (L×W×H)": "8.65 × 3.9 × 1.75 mm" } }, "sections": [@@ -182,6 +182,17 @@ "docs/hero.png", "docs/sn74hc74-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "sn74hc74-etched.step"+ ],+ "variants": [+ {+ "mpn": "SN74HC74D (SOIC-14, tube)",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC74DR (SOIC-14, tape & reel)",+ "kind": "packaging"+ } ] }
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CURVE() GEOMETRIC_REPRESENTATION_ITEM() +RATIONAL_B_SPLINE_CURVE((1.,0.5,1.,0.5,1.,0.5,1.)) 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CURVE() GEOMETRIC_REPRESENTATION_ITEM() +RATIONAL_B_SPLINE_CURVE((1.,0.5,1.,0.5,1.,0.5,1.)) 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