SN74HC74

@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sn74hc74",+  "title": "SN74HC74",+  "brief": "TI dual D-type positive-edge flip-flop, SOIC-14. Async preset/clear, HC CMOS, 2-6 V. Datasheet-verified.",   "version": "0.1.0",-  "type": "component",-  "description": "TI dual D-type positive-edge flip-flop, SOIC-14. Async preset/clear, HC CMOS, 2-6 V. Datasheet-verified.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",@@ -12,6 +15,157 @@     "soic-14",     "texas-instruments"   ],+  "component": {+    "mpn": "SN74HC74",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic IC",+    "subcategory": "Dual D flip-flop",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc74.pdf",+    "parts": {+      "symbol": "sn74hc74.kicad_sym",+      "footprint": "sn74hc74.kicad_mod",+      "model_3d": "sn74hc74.glb"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1CLR",+        "type": "input",+        "description": "Channel 1 asynchronous clear input, active low. Driving low forces 1Q low and 1Q\u0304 high regardless of CLK/D. VIL \u2264 1.35 V @ VCC=4.5 V; input clamp current \u00b120 mA max."+      },+      {+        "number": "2",+        "name": "1D",+        "type": "input",+        "description": "Channel 1 data input; sampled on the rising edge of 1CLK. Setup time 20 ns typ @ VCC=4.5 V, hold time 0 ns."+      },+      {+        "number": "3",+        "name": "1CLK",+        "type": "input",+        "description": "Channel 1 positive-edge-triggered clock input. Maximum clock frequency 31 MHz @ VCC=4.5 V, 36 MHz @ VCC=6 V."+      },+      {+        "number": "4",+        "name": "1PRE",+        "type": "input",+        "description": "Channel 1 asynchronous preset input, active low. Driving low forces 1Q high and 1Q\u0304 low regardless of CLK/D. Minimum pulse width 20 ns @ VCC=4.5 V."+      },+      {+        "number": "5",+        "name": "1Q",+        "type": "output",+        "description": "Channel 1 flip-flop output. Follows 1D at the rising edge of 1CLK. VOH \u2265 3.98 V @ IOH=-4 mA, VCC=4.5 V; propagation delay 20 ns typ from CLK."+      },+      {+        "number": "6",+        "name": "1Q\u0304",+        "type": "output",+        "description": "Channel 1 inverted flip-flop output, complement of 1Q."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Device ground reference (0 V)."+      },+      {+        "number": "8",+        "name": "2Q\u0304",+        "type": "output",+        "description": "Channel 2 inverted flip-flop output, complement of 2Q."+      },+      {+        "number": "9",+        "name": "2Q",+        "type": "output",+        "description": "Channel 2 flip-flop output. Follows 2D at the rising edge of 2CLK."+      },+      {+        "number": "10",+        "name": "2PRE",+        "type": "input",+        "description": "Channel 2 asynchronous preset input, active low. Driving low forces 2Q high and 2Q\u0304 low regardless of CLK/D."+      },+      {+        "number": "11",+        "name": "2CLK",+        "type": "input",+        "description": "Channel 2 positive-edge-triggered clock input."+      },+      {+        "number": "12",+        "name": "2D",+        "type": "input",+        "description": "Channel 2 data input; sampled on the rising edge of 2CLK."+      },+      {+        "number": "13",+        "name": "2CLR",+        "type": "input",+        "description": "Channel 2 asynchronous clear input, active low. Driving low forces 2Q low and 2Q\u0304 high regardless of CLK/D."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply. Operating range 2 V to 6 V (nom 5 V); absolute max 7 V. ICC \u2264 40 \u00b5A over temperature."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74hc74.pdf",+        "pages": 41,+        "sha256": "a60d59528e97fe91",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Dual D-type flip-flop",+      "Trigger": "Positive (rising) clock edge",+      "Async controls": "PRE + CLR (active-low)",+      "Outputs": "Q + Q (complementary)",+      "Logic family": "HC (high-speed CMOS)",+      "Supply voltage": "2-6 V",+      "Package": "SOIC-14",+      "Body (L\u00d7W\u00d7H)": "8.65 \u00d7 3.9 \u00d7 1.75 mm"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "sn74hc74",+    "74hc74",+    "dual d flip-flop",+    "d-type flip flop"+  ],+  "discovery_pitch": "SN74HC74 dual D-type positive-edge-triggered flip-flop (SOIC-14) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -27,10 +181,5 @@     "docs/sn74hc74-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file