component
SN74HC574PW
Public Made by Adomby adom
lingxingic SN74HC574PW LX Flip Flops, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+188−8@@ -1,13 +1,198 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc574pw",+ "title": "SN74HC574PW",+ "brief": "lingxingic SN74HC574PW LX Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "lingxingic SN74HC574PW LX Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74hc574pw" ],+ "component": {+ "mpn": "SN74HC574PW",+ "manufacturer": "lingxingic SN74HC574PW LX",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2404021111_lingxingic-SN74HC574PW-LX_C22374075.pdf",+ "parts": {+ "symbol": "sn74hc574pw.kicad_sym",+ "footprint": "sn74hc574pw.kicad_mod",+ "model_3d": "sn74hc574pw.glb",+ "model_3d_step": "sn74hc574pw.step",+ "lbr": "sn74hc574pw.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "/OE",+ "type": "input",+ "description": "3-state output enable, active low. When /OE = L the Q outputs are driven from the internal latch; when /OE = H all Q outputs enter high-impedance (Z). Does not affect the state of the internal latches."+ },+ {+ "number": "2",+ "name": "D0",+ "type": "input",+ "description": "Data input bit 0. Latched into internal flip-flop FF1 on the rising edge of CP; setup/hold timing per 3.3 electrical characteristics."+ },+ {+ "number": "3",+ "name": "D1",+ "type": "input",+ "description": "Data input bit 1. Latched into internal flip-flop FF2 on the rising edge of CP."+ },+ {+ "number": "4",+ "name": "D2",+ "type": "input",+ "description": "Data input bit 2. Latched into internal flip-flop FF3 on the rising edge of CP."+ },+ {+ "number": "5",+ "name": "D3",+ "type": "input",+ "description": "Data input bit 3. Latched into internal flip-flop FF4 on the rising edge of CP."+ },+ {+ "number": "6",+ "name": "D4",+ "type": "input",+ "description": "Data input bit 4. Latched into internal flip-flop FF5 on the rising edge of CP."+ },+ {+ "number": "7",+ "name": "D5",+ "type": "input",+ "description": "Data input bit 5. Latched into internal flip-flop FF6 on the rising edge of CP."+ },+ {+ "number": "8",+ "name": "D6",+ "type": "input",+ "description": "Data input bit 6. Latched into internal flip-flop FF7 on the rising edge of CP."+ },+ {+ "number": "9",+ "name": "D7",+ "type": "input",+ "description": "Data input bit 7. Latched into internal flip-flop FF8 on the rising edge of CP."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Return path for VCC."+ },+ {+ "number": "11",+ "name": "CP",+ "type": "input",+ "description": "Clock input, positive edge-triggered. All eight Dn inputs are transferred to the internal latches on the L->H transition of CP."+ },+ {+ "number": "12",+ "name": "Q7",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 7 (from FF8). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "13",+ "name": "Q6",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 6 (from FF7). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "14",+ "name": "Q5",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 5 (from FF6). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "15",+ "name": "Q4",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 4 (from FF5). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "16",+ "name": "Q3",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 3 (from FF4). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "17",+ "name": "Q2",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 2 (from FF3). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "18",+ "name": "Q1",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 1 (from FF2). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "19",+ "name": "Q0",+ "type": "tri_state",+ "description": "3-state flip-flop output bit 0 (from FF1). Driven when /OE = L; Hi-Z when /OE = H."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply. SN74HC574: 2.0-6.0 V (CMOS levels). SN74HCT574: 4.5-5.5 V (TTL-compatible input levels). Decouple to GND with 0.1 uF close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2404021111_lingxingic-SN74HC574PW-LX_C22374075.pdf",+ "pages": 20,+ "sha256": "4513b7374c86e098",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "lingxingic SN74HC574PW LX",+ "Package": "TSSOP-20",+ "Category": "Logic",+ "Pins": "20"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc574pw"+ ],+ "discovery_pitch": "SN74HC574PW (lingxingic SN74HC574PW LX) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +210,5 @@ "docs/sn74hc574pw-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }