component
SN74HC4040
Public Made by Adomby adom
TI 12-stage binary ripple counter, SOIC-16. Twelve outputs, clock + async clear, divides by up to 4096. Datasheet-verified.
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page.json+171−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc4040",+ "title": "SN74HC4040",+ "brief": "TI 12-stage binary ripple counter, SOIC-16. Twelve outputs, clock + async clear, divides by up to 4096. Datasheet-verified.", "version": "0.1.0",- "type": "component",- "description": "TI 12-stage binary ripple counter, SOIC-16. Twelve outputs, clock + async clear, divides by up to 4096. Datasheet-verified.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic",@@ -13,6 +16,171 @@ "soic-16", "texas-instruments" ],+ "component": {+ "mpn": "SN74HC4040",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic IC",+ "subcategory": "12-stage binary ripple counter",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc4040.pdf",+ "parts": {+ "symbol": "sn74hc4040.kicad_sym",+ "footprint": "sn74hc4040.kicad_mod",+ "model_3d": "sn74hc4040.glb"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "QL",+ "type": "output",+ "description": "Counter stage 12 output (Q12, MSB). Push-pull CMOS output, \u00b14 mA drive at 5 V. Toggles on the falling edge of stage 11's output; frequency = fCLK / 4096."+ },+ {+ "number": "2",+ "name": "QF",+ "type": "output",+ "description": "Counter stage 6 output (Q6). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 64."+ },+ {+ "number": "3",+ "name": "QE",+ "type": "output",+ "description": "Counter stage 5 output (Q5). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 32."+ },+ {+ "number": "4",+ "name": "QG",+ "type": "output",+ "description": "Counter stage 7 output (Q7). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 128."+ },+ {+ "number": "5",+ "name": "QD",+ "type": "output",+ "description": "Counter stage 4 output (Q4). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 16."+ },+ {+ "number": "6",+ "name": "QC",+ "type": "output",+ "description": "Counter stage 3 output (Q3). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 8."+ },+ {+ "number": "7",+ "name": "QB",+ "type": "output",+ "description": "Counter stage 2 output (Q2). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 4."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground / negative supply return. 0 V reference for VCC and all logic levels."+ },+ {+ "number": "9",+ "name": "QA",+ "type": "output",+ "description": "Counter stage 1 output (Q1, LSB). Push-pull CMOS output, \u00b14 mA drive at 5 V. Toggles on each falling edge of CLK; frequency = fCLK / 2."+ },+ {+ "number": "10",+ "name": "CLK",+ "type": "input",+ "description": "Clock input. Counter advances on the high-to-low (falling-edge) transition. Standard CMOS logic input: VIH \u2265 3.15 V and VIL \u2264 1.35 V at VCC = 4.5 V. Max clock frequency = 25 MHz at VCC = 6 V."+ },+ {+ "number": "11",+ "name": "CLR",+ "type": "input",+ "description": "Asynchronous master reset (active high). A high level asynchronously clears the counter and forces all Q outputs low, independent of CLK. Standard CMOS logic input."+ },+ {+ "number": "12",+ "name": "QI",+ "type": "output",+ "description": "Counter stage 9 output (Q9). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 512."+ },+ {+ "number": "13",+ "name": "QH",+ "type": "output",+ "description": "Counter stage 8 output (Q8). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 256."+ },+ {+ "number": "14",+ "name": "QJ",+ "type": "output",+ "description": "Counter stage 10 output (Q10). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 1024."+ },+ {+ "number": "15",+ "name": "QK",+ "type": "output",+ "description": "Counter stage 11 output (Q11). Push-pull CMOS output, \u00b14 mA drive at 5 V. Frequency = fCLK / 2048."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply input. Operating range 2 V to 6 V (absolute max 7 V). Bypass with a 0.1 \u00b5F ceramic close to the pin; a paralleled 1 \u00b5F is also recommended. ICC \u2264 80 \u00b5A (74HC) with static inputs."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74hc4040.pdf",+ "pages": 31,+ "sha256": "ad1231c1bceb2364",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "12-stage binary ripple counter",+ "Outputs": "12 (QA-QL, powers of two)",+ "Division": "divide-by-2 up to divide-by-4096",+ "Clock": "negative-edge triggered",+ "Reset": "asynchronous clear (active-high)",+ "Logic family": "HC (high-speed CMOS)",+ "Supply voltage": "2-6 V",+ "Package": "SOIC-16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc4040",+ "74hc4040",+ "12-stage counter",+ "binary ripple counter",+ "frequency divider",+ "cd4040"+ ],+ "discovery_pitch": "SN74HC4040 12-stage binary ripple counter (SOIC-16) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -28,10 +196,5 @@ "docs/sn74hc4040-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }