component
SN74HC393
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TI dual 4-bit binary ripple counter, SOIC-14. Two counters, clock + clear each, cascadable. HC CMOS 2-6 V. Datasheet-verified.
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page.json+158−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc393",+ "title": "SN74HC393",+ "brief": "TI dual 4-bit binary ripple counter, SOIC-14. Two counters, clock + clear each, cascadable. HC CMOS 2-6 V. Datasheet-verified.", "version": "0.1.0",- "type": "component",- "description": "TI dual 4-bit binary ripple counter, SOIC-14. Two counters, clock + clear each, cascadable. HC CMOS 2-6 V. Datasheet-verified.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic",@@ -12,6 +15,158 @@ "soic-14", "texas-instruments" ],+ "component": {+ "mpn": "SN74HC393",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic IC",+ "subcategory": "Dual 4-bit binary counter",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc393.pdf",+ "parts": {+ "symbol": "sn74hc393.kicad_sym",+ "footprint": "sn74hc393.kicad_mod",+ "model_3d": "sn74hc393.glb"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "1CLK",+ "type": "input",+ "description": "Counter 1 clock input. Counter 1 advances on the high-to-low (falling-edge) transition of this input. CMOS-level input, 2 V to 6 V logic swing; typical clock frequency 31 MHz at VCC=4.5 V."+ },+ {+ "number": "2",+ "name": "1CLR",+ "type": "input",+ "description": "Counter 1 asynchronous clear input, active high. When held high, Q1A-Q1D are forced low regardless of 1CLK. Minimum high pulse width ~16 ns at VCC=4.5 V."+ },+ {+ "number": "3",+ "name": "1QA",+ "type": "output",+ "description": "Counter 1 stage A (LSB) output. Toggles on each falling edge of 1CLK; divides input clock by 2. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "4",+ "name": "1QB",+ "type": "output",+ "description": "Counter 1 stage B output. Toggles on each falling edge of 1QA; divides 1CLK by 4. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "5",+ "name": "1QC",+ "type": "output",+ "description": "Counter 1 stage C output. Toggles on each falling edge of 1QB; divides 1CLK by 8. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "6",+ "name": "1QD",+ "type": "output",+ "description": "Counter 1 stage D (MSB) output. Toggles on each falling edge of 1QC; divides 1CLK by 16. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Return path for VCC current."+ },+ {+ "number": "8",+ "name": "2QD",+ "type": "output",+ "description": "Counter 2 stage D (MSB) output. Toggles on each falling edge of 2QC; divides 2CLK by 16. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "9",+ "name": "2QC",+ "type": "output",+ "description": "Counter 2 stage C output. Toggles on each falling edge of 2QB; divides 2CLK by 8. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "10",+ "name": "2QB",+ "type": "output",+ "description": "Counter 2 stage B output. Toggles on each falling edge of 2QA; divides 2CLK by 4. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "11",+ "name": "2QA",+ "type": "output",+ "description": "Counter 2 stage A (LSB) output. Toggles on each falling edge of 2CLK; divides input clock by 2. Push-pull CMOS output, \u00b14 mA drive at VCC=5 V."+ },+ {+ "number": "12",+ "name": "2CLR",+ "type": "input",+ "description": "Counter 2 asynchronous clear input, active high. When held high, Q2A-Q2D are forced low regardless of 2CLK. Minimum high pulse width ~16 ns at VCC=4.5 V."+ },+ {+ "number": "13",+ "name": "2CLK",+ "type": "input",+ "description": "Counter 2 clock input. Counter 2 advances on the high-to-low (falling-edge) transition of this input. CMOS-level input, 2 V to 6 V logic swing."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply. Recommended 2 V to 6 V (5 V nominal). Bypass to GND with 0.1 \u00b5F (and optional 1 \u00b5F) placed close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74hc393.pdf",+ "pages": 38,+ "sha256": "aa77c46be80d7142",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "Dual 4-bit binary counter",+ "Counters": "2 independent (4-bit each)",+ "Clock": "negative-edge triggered",+ "Reset": "active-high clear per counter",+ "Cascade": "QD to next CLK (8-bit and beyond)",+ "Logic family": "HC (high-speed CMOS)",+ "Supply voltage": "2-6 V",+ "Package": "SOIC-14"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc393",+ "74hc393",+ "dual binary counter",+ "4-bit counter",+ "ripple counter"+ ],+ "discovery_pitch": "SN74HC393 dual 4-bit binary ripple counter (SOIC-14) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +182,5 @@ "docs/sn74hc393-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }