component
SN74HC377DWR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+22−19@@ -38,55 +38,55 @@ "number": "2", "name": "1Q", "type": "output",- "description": "Flip-flop 1 single-rail data output. Follows 1D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 1 single-rail data output. Follows 1D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "3", "name": "1D", "type": "input",- "description": "Flip-flop 1 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 1 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "4", "name": "2D", "type": "input",- "description": "Flip-flop 2 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 2 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "5", "name": "2Q", "type": "output",- "description": "Flip-flop 2 single-rail data output. Follows 2D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 2 single-rail data output. Follows 2D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "6", "name": "3Q", "type": "output",- "description": "Flip-flop 3 single-rail data output. Follows 3D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 3 single-rail data output. Follows 3D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "7", "name": "3D", "type": "input",- "description": "Flip-flop 3 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 3 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "8", "name": "4D", "type": "input",- "description": "Flip-flop 4 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 4 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "9", "name": "4Q", "type": "output",- "description": "Flip-flop 4 single-rail data output. Follows 4D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 4 single-rail data output. Follows 4D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "10", "name": "GND", "type": "power_in",- "description": "Device ground return. Tie to system 0 V. Continuous current through GND limited to \u00b150 mA (absolute max)."+ "description": "Device ground return. Tie to system 0 V. Continuous current through GND limited to ±50 mA (absolute max)." }, { "number": "11",@@ -98,55 +98,55 @@ "number": "12", "name": "5Q", "type": "output",- "description": "Flip-flop 5 single-rail data output. Follows 5D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 5 single-rail data output. Follows 5D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "13", "name": "5D", "type": "input",- "description": "Flip-flop 5 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 5 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "14", "name": "6D", "type": "input",- "description": "Flip-flop 6 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 6 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "15", "name": "6Q", "type": "output",- "description": "Flip-flop 6 single-rail data output. Follows 6D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 6 single-rail data output. Follows 6D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "16", "name": "7Q", "type": "output",- "description": "Flip-flop 7 single-rail data output. Follows 7D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 7 single-rail data output. Follows 7D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "17", "name": "7D", "type": "input",- "description": "Flip-flop 7 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 7 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "18", "name": "8D", "type": "input",- "description": "Flip-flop 8 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = \u00b11 \u00b5A max)."+ "description": "Flip-flop 8 data input. Sampled on the rising edge of CLK when CLKEN is low. High-impedance CMOS input (II = ±1 µA max)." }, { "number": "19", "name": "8Q", "type": "output",- "description": "Flip-flop 8 single-rail data output. Follows 8D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated \u00b14 mA at VCC = 5 V."+ "description": "Flip-flop 8 single-rail data output. Follows 8D on the rising edge of CLK when CLKEN is low. CMOS push-pull output rated ±4 mA at VCC = 5 V." }, { "number": "20", "name": "VCC", "type": "power_in",- "description": "Positive supply. Recommended operating range 2 V to 6 V; absolute maximum -0.5 V to 7 V. Typical ICC = 80 \u00b5A max (SN74HC377) at VI = VCC or 0."+ "description": "Positive supply. Recommended operating range 2 V to 6 V; absolute maximum -0.5 V to 7 V. Typical ICC = 80 µA max (SN74HC377) at VI = VCC or 0." } ], "provenance": {@@ -210,5 +210,8 @@ "docs/sn74hc377dwr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }