component
SN74HC373
Public Made by Adomby adom
TI octal transparent D latch with 3-state outputs, SOIC-20. Latch-enable + output-enable, 2-6 V. Datasheet-verified.
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page.json+194−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc373",+ "title": "SN74HC373",+ "brief": "TI octal transparent D latch with 3-state outputs, SOIC-20. Latch-enable + output-enable, 2-6 V. Datasheet-verified.", "version": "0.1.0",- "type": "component",- "description": "TI octal transparent D latch with 3-state outputs, SOIC-20. Latch-enable + output-enable, 2-6 V. Datasheet-verified.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic",@@ -12,6 +15,194 @@ "soic-20", "texas-instruments" ],+ "component": {+ "mpn": "SN74HC373",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20",+ "pin_count": 20,+ "category": "Logic IC",+ "subcategory": "Octal transparent D latch (3-state)",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc373.pdf",+ "parts": {+ "symbol": "sn74hc373.kicad_sym",+ "footprint": "sn74hc373.kicad_mod",+ "model_3d": "sn74hc373.glb"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Active-low output enable. When low, the Q outputs are actively driven; when high, all Q outputs are placed in the high-impedance (3-state) state. Does not affect the stored latch state."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 1. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Data input for latch channel 1. Passes to 1Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Data input for latch channel 2. Passes to 2Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 2. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 3. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Data input for latch channel 3. Passes to 3Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Data input for latch channel 4. Passes to 4Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 4. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V) for the device."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch enable, common to all eight latches. When high, Q outputs transparently follow D inputs; when driven low, the D-input state at the falling edge is latched at the outputs. Setup time 15 ns and hold time 13 ns at 4.5 V."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 5. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Data input for latch channel 5. Passes to 5Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Data input for latch channel 6. Passes to 6Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 6. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 7. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Data input for latch channel 7. Passes to 7Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Data input for latch channel 8. Passes to 8Q while LE is high; captured on LE falling edge."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "tri_state",+ "description": "3-state output for latch channel 8. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply. Recommended operating range 2 V to 6 V (absolute max 7 V). Bypass with a local 0.1 \u00b5F ceramic to GND."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74hc373.pdf",+ "pages": 38,+ "sha256": "09faaa55733b1ac6",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "Octal transparent D latch, 3-state",+ "Latches": "8",+ "Latch enable": "LE (transparent high, hold low)",+ "Output enable": "/OE (active-low, Hi-Z)",+ "Logic family": "HC (high-speed CMOS)",+ "Supply voltage": "2-6 V",+ "Package": "SOIC-20",+ "Body (L\u00d7W\u00d7H)": "12.8 \u00d7 7.5 \u00d7 2.35 mm"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc373",+ "74hc373",+ "octal latch",+ "transparent latch",+ "address latch"+ ],+ "discovery_pitch": "SN74HC373 octal transparent D latch with 3-state outputs (SOIC-20) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +218,5 @@ "docs/sn74hc373-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }