component
SN74HC373
Public Made by Adomby adom
TI octal transparent D latch with 3-state outputs, SOIC-20. Latch-enable + output-enable, 2-6 V. Datasheet-verified.
← Commit history
sn74hc373: backfill missing artifacts (etch, variants)
3 files changed
+22248−11
diff truncated
README.md+2@@ -44,6 +44,8 @@ Eight transparent D-type latches with 3-state outputs in a SOIC-20. While the la ## Ordering variants +Same part, different packaging or reel option.+ - `SN74HC373DW (SOIC-20, tube)` - `SN74HC373DWR (SOIC-20, tape & reel)`
page.json+22−11@@ -41,7 +41,7 @@ "number": "2", "name": "1Q", "type": "tri_state",- "description": "3-state output for latch channel 1. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 1. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "3",@@ -59,13 +59,13 @@ "number": "5", "name": "2Q", "type": "tri_state",- "description": "3-state output for latch channel 2. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 2. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "6", "name": "3Q", "type": "tri_state",- "description": "3-state output for latch channel 3. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 3. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "7",@@ -83,7 +83,7 @@ "number": "9", "name": "4Q", "type": "tri_state",- "description": "3-state output for latch channel 4. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 4. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "10",@@ -101,7 +101,7 @@ "number": "12", "name": "5Q", "type": "tri_state",- "description": "3-state output for latch channel 5. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 5. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "13",@@ -119,13 +119,13 @@ "number": "15", "name": "6Q", "type": "tri_state",- "description": "3-state output for latch channel 6. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 6. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "16", "name": "7Q", "type": "tri_state",- "description": "3-state output for latch channel 7. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 7. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "17",@@ -143,13 +143,13 @@ "number": "19", "name": "8Q", "type": "tri_state",- "description": "3-state output for latch channel 8. Drives \u00b16 mA at 5 V; enters Hi-Z when OE is high."+ "description": "3-state output for latch channel 8. Drives ±6 mA at 5 V; enters Hi-Z when OE is high." }, { "number": "20", "name": "VCC", "type": "power_in",- "description": "Positive supply. Recommended operating range 2 V to 6 V (absolute max 7 V). Bypass with a local 0.1 \u00b5F ceramic to GND."+ "description": "Positive supply. Recommended operating range 2 V to 6 V (absolute max 7 V). Bypass with a local 0.1 µF ceramic to GND." } ], "provenance": {@@ -182,7 +182,7 @@ "Logic family": "HC (high-speed CMOS)", "Supply voltage": "2-6 V", "Package": "SOIC-20",- "Body (L\u00d7W\u00d7H)": "12.8 \u00d7 7.5 \u00d7 2.35 mm"+ "Body (L×W×H)": "12.8 × 7.5 × 2.35 mm" } }, "sections": [@@ -219,6 +219,17 @@ "docs/hero.png", "docs/sn74hc373-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "sn74hc373-etched.step"+ ],+ "variants": [+ {+ "mpn": "SN74HC373DW (SOIC-20, tube)",+ "kind": "packaging"+ },+ {+ "mpn": "SN74HC373DWR (SOIC-20, tape & reel)",+ "kind": "packaging"+ } ] }
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CURVE() GEOMETRIC_REPRESENTATION_ITEM() +RATIONAL_B_SPLINE_CURVE((1.,0.5,1.,0.5,1.,0.5,1.)) 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