component
SN74HC273PW
Public Made by Adomby adom
lingxingic SN74HC273PW LX Flip Flops, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+188−8@@ -1,13 +1,198 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc273pw",+ "title": "SN74HC273PW",+ "brief": "lingxingic SN74HC273PW LX Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "lingxingic SN74HC273PW LX Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74hc273pw" ],+ "component": {+ "mpn": "SN74HC273PW",+ "manufacturer": "lingxingic SN74HC273PW LX",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2404021112_lingxingic-SN74HC273PW-LX_C22374055.pdf",+ "parts": {+ "symbol": "sn74hc273pw.kicad_sym",+ "footprint": "sn74hc273pw.kicad_mod",+ "model_3d": "sn74hc273pw.glb",+ "model_3d_step": "sn74hc273pw.step",+ "lbr": "sn74hc273pw.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "MR",+ "type": "input",+ "description": "Active-low master reset input. When driven low, all eight Qn outputs are forced low asynchronously, regardless of the clock or data inputs."+ },+ {+ "number": "2",+ "name": "Q0",+ "type": "output",+ "description": "Flip-flop 0 output. Follows D0 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "input",+ "description": "Data input 0. Sampled by flip-flop 0 on the rising edge of CP."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Data input 1. Sampled by flip-flop 1 on the rising edge of CP."+ },+ {+ "number": "5",+ "name": "Q1",+ "type": "output",+ "description": "Flip-flop 1 output. Follows D1 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "6",+ "name": "Q2",+ "type": "output",+ "description": "Flip-flop 2 output. Follows D2 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "7",+ "name": "D2",+ "type": "input",+ "description": "Data input 2. Sampled by flip-flop 2 on the rising edge of CP."+ },+ {+ "number": "8",+ "name": "D3",+ "type": "input",+ "description": "Data input 3. Sampled by flip-flop 3 on the rising edge of CP."+ },+ {+ "number": "9",+ "name": "Q3",+ "type": "output",+ "description": "Flip-flop 3 output. Follows D3 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, 0 V."+ },+ {+ "number": "11",+ "name": "CP",+ "type": "input",+ "description": "Clock input, rising-edge triggered. On the low-to-high transition all eight Dn inputs are latched into their respective Qn outputs."+ },+ {+ "number": "12",+ "name": "Q4",+ "type": "output",+ "description": "Flip-flop 4 output. Follows D4 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "13",+ "name": "D4",+ "type": "input",+ "description": "Data input 4. Sampled by flip-flop 4 on the rising edge of CP."+ },+ {+ "number": "14",+ "name": "D5",+ "type": "input",+ "description": "Data input 5. Sampled by flip-flop 5 on the rising edge of CP."+ },+ {+ "number": "15",+ "name": "Q5",+ "type": "output",+ "description": "Flip-flop 5 output. Follows D5 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "16",+ "name": "Q6",+ "type": "output",+ "description": "Flip-flop 6 output. Follows D6 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "17",+ "name": "D6",+ "type": "input",+ "description": "Data input 6. Sampled by flip-flop 6 on the rising edge of CP."+ },+ {+ "number": "18",+ "name": "D7",+ "type": "input",+ "description": "Data input 7. Sampled by flip-flop 7 on the rising edge of CP."+ },+ {+ "number": "19",+ "name": "Q7",+ "type": "output",+ "description": "Flip-flop 7 output. Follows D7 on the rising edge of CP; forced low when MR is asserted."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. Recommended operating range per HC/HCT family (typically 2 V to 6 V for HC)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2404021112_lingxingic-SN74HC273PW-LX_C22374055.pdf",+ "pages": 27,+ "sha256": "a26108f4267548db",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "lingxingic SN74HC273PW LX",+ "Package": "TSSOP-20",+ "Category": "Logic",+ "Pins": "20"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc273pw"+ ],+ "discovery_pitch": "SN74HC273PW (lingxingic SN74HC273PW LX) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +210,5 @@ "docs/sn74hc273pw-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }