SN74HC273PW

@@ -0,0 +1,63 @@+# SN74HC273PW++**lingxingic SN74HC273PW LX** · Flip Flops · TSSOP-20++SN74HC273PW from lingxingic SN74HC273PW LX, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MR | input | Active-low master reset input. When driven low, all eight Qn outputs are forced low asynchronously, regardless of the clock or data inputs. |+| 2 | Q0 | output | Flip-flop 0 output. Follows D0 on the rising edge of CP; forced low when MR is asserted. |+| 3 | D0 | input | Data input 0. Sampled by flip-flop 0 on the rising edge of CP. |+| 4 | D1 | input | Data input 1. Sampled by flip-flop 1 on the rising edge of CP. |+| 5 | Q1 | output | Flip-flop 1 output. Follows D1 on the rising edge of CP; forced low when MR is asserted. |+| 6 | Q2 | output | Flip-flop 2 output. Follows D2 on the rising edge of CP; forced low when MR is asserted. |+| 7 | D2 | input | Data input 2. Sampled by flip-flop 2 on the rising edge of CP. |+| 8 | D3 | input | Data input 3. Sampled by flip-flop 3 on the rising edge of CP. |+| 9 | Q3 | output | Flip-flop 3 output. Follows D3 on the rising edge of CP; forced low when MR is asserted. |+| 10 | GND | power_in | Ground reference, 0 V. |+| 11 | CP | input | Clock input, rising-edge triggered. On the low-to-high transition all eight Dn inputs are latched into their respective Qn outputs. |+| 12 | Q4 | output | Flip-flop 4 output. Follows D4 on the rising edge of CP; forced low when MR is asserted. |+| 13 | D4 | input | Data input 4. Sampled by flip-flop 4 on the rising edge of CP. |+| 14 | D5 | input | Data input 5. Sampled by flip-flop 5 on the rising edge of CP. |+| 15 | Q5 | output | Flip-flop 5 output. Follows D5 on the rising edge of CP; forced low when MR is asserted. |+| 16 | Q6 | output | Flip-flop 6 output. Follows D6 on the rising edge of CP; forced low when MR is asserted. |+| 17 | D6 | input | Data input 6. Sampled by flip-flop 6 on the rising edge of CP. |+| 18 | D7 | input | Data input 7. Sampled by flip-flop 7 on the rising edge of CP. |+| 19 | Q7 | output | Flip-flop 7 output. Follows D7 on the rising edge of CP; forced low when MR is asserted. |+| 20 | VCC | power_in | Supply voltage. Recommended operating range per HC/HCT family (typically 2 V to 6 V for HC). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | lingxingic SN74HC273PW LX |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## Ordering variants++- `SN74HC273PW`+- `SN74HC273PWN`+- `SN74HC273PWD`+- `SN74HC273PWNSR`++## CAD (KiCad official)++- Symbol: `SN74HC273PW`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [lingxingic SN74HC273PW LX datasheet](docs/sn74hc273pw-datasheet.pdf) (27 pp, sha256 `a26108f4267548db`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hc273pw-datasheet.pdf)

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