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Set visibility: public

Ray ·7d3ffae304 · ·parent 6bd992a
1 file changed +8−5
page.json+8−5
@@ -32,7 +32,7 @@         "number": "1",         "name": "1A",         "type": "input",-        "description": "Channel 1, Input A. CMOS logic input to gate 1 (VIH \u2265 3.15 V @ VCC = 4.5 V; VIL \u2264 1.35 V @ VCC = 4.5 V)."+        "description": "Channel 1, Input A. CMOS logic input to gate 1 (VIH ≥ 3.15 V @ VCC = 4.5 V; VIL ≤ 1.35 V @ VCC = 4.5 V)."       },       {         "number": "2",@@ -62,7 +62,7 @@         "number": "6",         "name": "1Y",         "type": "output",-        "description": "Channel 1, Output Y. 1Y = 1A \u00b7 1B \u00b7 1C \u00b7 1D. CMOS push-pull output; IOL/IOH up to \u00b15.2 mA at VCC = 6 V."+        "description": "Channel 1, Output Y. 1Y = 1A · 1B · 1C · 1D. CMOS push-pull output; IOL/IOH up to ±5.2 mA at VCC = 6 V."       },       {         "number": "7",@@ -74,7 +74,7 @@         "number": "8",         "name": "2Y",         "type": "output",-        "description": "Channel 2, Output Y. 2Y = 2A \u00b7 2B \u00b7 2C \u00b7 2D. CMOS push-pull output; IOL/IOH up to \u00b15.2 mA at VCC = 6 V."+        "description": "Channel 2, Output Y. 2Y = 2A · 2B · 2C · 2D. CMOS push-pull output; IOL/IOH up to ±5.2 mA at VCC = 6 V."       },       {         "number": "9",@@ -110,7 +110,7 @@         "number": "14",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply, 2 V to 6 V (absolute maximum 7 V). Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+        "description": "Positive supply, 2 V to 6 V (absolute maximum 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."       }     ],     "provenance": {@@ -174,5 +174,8 @@     "docs/sn74hc21dr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file