← Commit history

Publish 0.2.0

Ray ·71055e49c3 · ·parent 7a26479
3 files changed +24−10
README.md+14
@@ -48,6 +48,20 @@ SN74HC21DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions ext - Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm` - 3D model: SOIC-14 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74hc21dr.step`](sn74hc21dr.step) | 195 KB | You want the bare part, or you mark your own boards. |+| [`sn74hc21dr-etched.step`](sn74hc21dr-etched.step) | 2.2 MB | You want the part with `SN74HC21DR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 558 faces against 237 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1
@@ -1,6 +1,6 @@ {   "slug": "sn74hc21dr",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [
page.json+9−9
@@ -4,7 +4,7 @@   "slug": "sn74hc21dr",   "title": "SN74HC21DR",   "brief": "Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -36,7 +36,7 @@         "number": "1",         "name": "1A",         "type": "input",-        "description": "Channel 1, Input A. CMOS logic input to gate 1 (VIH \u2265 3.15 V @ VCC = 4.5 V; VIL \u2264 1.35 V @ VCC = 4.5 V)."+        "description": "Channel 1, Input A. CMOS logic input to gate 1 (VIH ≥ 3.15 V @ VCC = 4.5 V; VIL ≤ 1.35 V @ VCC = 4.5 V)."       },       {         "number": "2",@@ -66,7 +66,7 @@         "number": "6",         "name": "1Y",         "type": "output",-        "description": "Channel 1, Output Y. 1Y = 1A \u00b7 1B \u00b7 1C \u00b7 1D. CMOS push-pull output; IOL/IOH up to \u00b15.2 mA at VCC = 6 V."+        "description": "Channel 1, Output Y. 1Y = 1A · 1B · 1C · 1D. CMOS push-pull output; IOL/IOH up to ±5.2 mA at VCC = 6 V."       },       {         "number": "7",@@ -78,7 +78,7 @@         "number": "8",         "name": "2Y",         "type": "output",-        "description": "Channel 2, Output Y. 2Y = 2A \u00b7 2B \u00b7 2C \u00b7 2D. CMOS push-pull output; IOL/IOH up to \u00b15.2 mA at VCC = 6 V."+        "description": "Channel 2, Output Y. 2Y = 2A · 2B · 2C · 2D. CMOS push-pull output; IOL/IOH up to ±5.2 mA at VCC = 6 V."       },       {         "number": "9",@@ -114,7 +114,7 @@         "number": "14",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply, 2 V to 6 V (absolute maximum 7 V). Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+        "description": "Positive supply, 2 V to 6 V (absolute maximum 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."       }     ],     "provenance": {@@ -188,9 +188,9 @@     "docs/hero.png",     "docs/sn74hc21dr-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "Texas Instruments Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D." }\ No newline at end of file