component
SN74HC194 Universal Shift Register
Public Made by Adomby adom
4-bit bidirectional universal shift register with parallel load and shift-left/right control.
← Commit history
page.json+168−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc194",+ "title": "SN74HC194 Universal Shift Register",+ "brief": "4-bit bidirectional universal shift register with parallel load and shift-left/right control.", "version": "0.1.0",- "type": "component",- "description": "4-bit bidirectional universal shift register with parallel load and shift-left/right control.",+ "license": "CC-BY-SA-4.0", "tags": [ "logic", "shift-register",@@ -12,6 +15,168 @@ "ti", "soic-16" ],+ "component": {+ "mpn": "SN74HC194",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Register",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd74hc194.pdf",+ "parts": {+ "symbol": "sn74hc194.kicad_sym",+ "footprint": "sn74hc194.kicad_mod",+ "model_3d": "sn74hc194.glb"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "MR",+ "type": "input",+ "description": "Asynchronous Master Reset, active-low. When driven low, all four internal flip-flops are cleared and Q0-Q3 are forced to logic Low regardless of the clock. Minimum MR pulse width is 16ns at VCC=4.5V."+ },+ {+ "number": "2",+ "name": "DSR",+ "type": "input",+ "description": "Serial data input for shift-right mode. The logic level on DSR is clocked into Q0 on the rising edge of CP when S1=Low, S0=High."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "input",+ "description": "Parallel data input D0. Loaded into flip-flop Q0 on the rising edge of CP when S0=High and S1=High (parallel load mode)."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Parallel data input D1. Loaded into flip-flop Q1 on the rising edge of CP when S0=High and S1=High (parallel load mode)."+ },+ {+ "number": "5",+ "name": "D2",+ "type": "input",+ "description": "Parallel data input D2. Loaded into flip-flop Q2 on the rising edge of CP when S0=High and S1=High (parallel load mode)."+ },+ {+ "number": "6",+ "name": "D3",+ "type": "input",+ "description": "Parallel data input D3. Loaded into flip-flop Q3 on the rising edge of CP when S0=High and S1=High (parallel load mode)."+ },+ {+ "number": "7",+ "name": "DSL",+ "type": "input",+ "description": "Serial data input for shift-left mode. The logic level on DSL is clocked into Q3 on the rising edge of CP when S1=High, S0=Low."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0V) for the device."+ },+ {+ "number": "9",+ "name": "S0",+ "type": "input",+ "description": "Mode select input S0. Combined with S1 selects one of four operating modes: hold (S1=L,S0=L), shift-right (S1=L,S0=H), shift-left (S1=H,S0=L), parallel load (S1=H,S0=H)."+ },+ {+ "number": "10",+ "name": "S1",+ "type": "input",+ "description": "Mode select input S1. See S0 for the mode encoding table."+ },+ {+ "number": "11",+ "name": "CP",+ "type": "input",+ "description": "Clock input. All synchronous operations (shift-right, shift-left, parallel-load, hold) occur on the rising (Low-to-High) edge of CP. Typical fMAX = 60MHz at VCC=5V, CL=15pF."+ },+ {+ "number": "12",+ "name": "Q3",+ "type": "output",+ "description": "Parallel output Q3, the MSB of the shift register. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."+ },+ {+ "number": "13",+ "name": "Q2",+ "type": "output",+ "description": "Parallel output Q2. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."+ },+ {+ "number": "14",+ "name": "Q1",+ "type": "output",+ "description": "Parallel output Q1. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."+ },+ {+ "number": "15",+ "name": "Q0",+ "type": "output",+ "description": "Parallel output Q0, the LSB of the shift register. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. 2V to 6V for HC types, 4.5V to 5.5V for HCT types. Bypass with a 100nF ceramic capacitor close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd74hc194.pdf",+ "pages": 19,+ "sha256": "209a444fe7a9beeb",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "4-bit bidirectional universal shift register",+ "Logic family": "74HC (CMOS)",+ "Modes": "Shift left, shift right, parallel load, hold",+ "Clear": "Active-low, asynchronous",+ "Supply voltage": "2 V to 6 V",+ "Max clock": "50 MHz typ at 5 V",+ "Operating temperature": "-40 C to 85 C"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "universal shift register",+ "bidirectional shift register",+ "parallel load shift",+ "shift left right"+ ],+ "discovery_pitch": "A 4-bit register that shifts left, shifts right, parallel-loads, or holds under two mode pins.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +192,5 @@ "docs/sn74hc194-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }