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sn74hc164pwr: factory component page (tier=mfr)

Ray ·f56b3f2deb · ·parent 6275cda
1 file changed +152−8
page.json+152−8
@@ -1,13 +1,162 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sn74hc164pwr",+  "title": "SN74HC164PWR",+  "brief": "Texas Instruments Shifting Register, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Shifting Register, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "sn74hc164pwr"   ],+  "component": {+    "mpn": "SN74HC164PWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Shifting Register",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc164.pdf",+    "parts": {+      "symbol": "sn74hc164pwr.kicad_sym",+      "footprint": "sn74hc164pwr.kicad_mod",+      "model_3d": "sn74hc164pwr.glb",+      "model_3d_step": "sn74hc164pwr.step",+      "lbr": "sn74hc164pwr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Gated Serial Input 1. AND-gated with input B to form the serial data into the first flip-flop; a low on A inhibits new data entry and resets the first flip-flop on the next CLK rising edge. VIH min 1.5 V at VCC=2 V, 3.15 V at VCC=4.5 V."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Gated Serial Input 2. AND-gated with input A to form the serial data into the first flip-flop; a low on B inhibits new data entry. Input current \u00b11 \u00b5A max."+      },+      {+        "number": "3",+        "name": "QA",+        "type": "output",+        "description": "Parallel output bit A (first stage of the shift register). Drives \u00b14 mA at VCC=5 V into 10 LSTTL loads."+      },+      {+        "number": "4",+        "name": "QB",+        "type": "output",+        "description": "Parallel output bit B (second stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "5",+        "name": "QC",+        "type": "output",+        "description": "Parallel output bit C (third stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "6",+        "name": "QD",+        "type": "output",+        "description": "Parallel output bit D (fourth stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V)."+      },+      {+        "number": "8",+        "name": "CLK",+        "type": "input",+        "description": "Clock input. Data is shifted one position on the low-to-high transition; fmax up to 36 MHz typical at VCC=6 V. Minimum high/low pulse width 14 ns at 6 V."+      },+      {+        "number": "9",+        "name": "CLR",+        "type": "input",+        "description": "Asynchronous active-low clear. Driving CLR low forces all Q outputs (QA..QH) to logic 0 independent of CLK. Minimum low pulse width 17 ns at VCC=6 V."+      },+      {+        "number": "10",+        "name": "QE",+        "type": "output",+        "description": "Parallel output bit E (fifth stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "11",+        "name": "QF",+        "type": "output",+        "description": "Parallel output bit F (sixth stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "12",+        "name": "QG",+        "type": "output",+        "description": "Parallel output bit G (seventh stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "13",+        "name": "QH",+        "type": "output",+        "description": "Parallel output bit H (eighth/last stage of the shift register). CMOS push-pull output; \u00b14 mA drive at 5 V."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage, 2 V to 6 V (recommended 5 V nominal). ICC max 8 \u00b5A at 25 \u00b0C."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74hc164.pdf",+        "pages": 38,+        "sha256": "51860c45fddf000a",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "TSSOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "sn74hc164pwr"+  ],+  "discovery_pitch": "SN74HC164PWR (Texas Instruments) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +174,5 @@     "docs/sn74hc164pwr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file