component
SN74HC161DR
Public Made by Adomby adom
Texas Instruments Counters / Dividers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74hc161dr",+ "title": "SN74HC161DR",+ "brief": "Texas Instruments Counters / Dividers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Counters / Dividers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74hc161dr" ],+ "component": {+ "mpn": "SN74HC161DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters / Dividers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc161.pdf",+ "parts": {+ "symbol": "sn74hc161dr.kicad_sym",+ "footprint": "sn74hc161dr.kicad_mod",+ "model_3d": "sn74hc161dr.glb",+ "model_3d_step": "sn74hc161dr.step",+ "lbr": "sn74hc161dr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear. Driving CLR low forces all four Q outputs (QA-QD) low regardless of CLK, LOAD, or enable states."+ },+ {+ "number": "2",+ "name": "CLK",+ "type": "input",+ "description": "Buffered clock input. All four internal D/T flip-flops are triggered on the rising (positive-going) edge of CLK. Max clock frequency is ~25 MHz at Vcc=4.5 V."+ },+ {+ "number": "3",+ "name": "A",+ "type": "input",+ "description": "Parallel data input A (LSB of the 4-bit preset value). Loaded synchronously into the QA flip-flop on the rising edge of CLK when LOAD is low."+ },+ {+ "number": "4",+ "name": "B",+ "type": "input",+ "description": "Parallel data input B. Loaded synchronously into the QB flip-flop on the rising edge of CLK when LOAD is low."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Parallel data input C. Loaded synchronously into the QC flip-flop on the rising edge of CLK when LOAD is low."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Parallel data input D (MSB of the 4-bit preset value). Loaded synchronously into the QD flip-flop on the rising edge of CLK when LOAD is low."+ },+ {+ "number": "7",+ "name": "ENP",+ "type": "input",+ "description": "Count enable (P). Must be high, together with ENT, to enable counting on the next CLK rising edge. Transitions on ENP are allowed regardless of CLK state."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V) for the device."+ },+ {+ "number": "9",+ "name": "LOAD",+ "type": "input",+ "description": "Active-low synchronous parallel-load input. A low level disables counting and forces QA-QD to match the A-D inputs on the next rising edge of CLK."+ },+ {+ "number": "10",+ "name": "ENT",+ "type": "input",+ "description": "Count enable (T). Must be high, together with ENP, to enable counting; ENT is also fed forward to gate the RCO output. Transitions on ENT are allowed regardless of CLK state."+ },+ {+ "number": "11",+ "name": "QD",+ "type": "output",+ "description": "Counter output bit D (MSB). Push-pull CMOS output capable of driving \u00b14 mA at Vcc=5 V (up to 10 LSTTL loads)."+ },+ {+ "number": "12",+ "name": "QC",+ "type": "output",+ "description": "Counter output bit C. Push-pull CMOS output capable of driving \u00b14 mA at Vcc=5 V."+ },+ {+ "number": "13",+ "name": "QB",+ "type": "output",+ "description": "Counter output bit B. Push-pull CMOS output capable of driving \u00b14 mA at Vcc=5 V."+ },+ {+ "number": "14",+ "name": "QA",+ "type": "output",+ "description": "Counter output bit A (LSB). Push-pull CMOS output capable of driving \u00b14 mA at Vcc=5 V."+ },+ {+ "number": "15",+ "name": "RCO",+ "type": "output",+ "description": "Ripple-carry output. Produces a high-level pulse (gated by ENT) when the count reaches its maximum value (15, with QA high), used to cascade successive counter stages for n-bit synchronous counting."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, 2 V to 6 V recommended operating range (absolute max 7 V). Typical Icc is 80 \u00b5A max for the 74HC variant."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74hc161.pdf",+ "pages": 31,+ "sha256": "58fced3e842dd1c0",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "SOIC-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74hc161dr"+ ],+ "discovery_pitch": "SN74HC161DR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/sn74hc161dr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }