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Set visibility: public

Ray ·91b5a33f06 ·1mo ago ·parent 0431384
1 file changed +11−8
page.json+11−8
@@ -32,19 +32,19 @@         "number": "1",         "name": "1A",         "type": "input",-        "description": "Channel 1, Input A. Standard high-impedance CMOS input to gate 1; VIH \u2265 3.15 V and VIL \u2264 1.35 V at VCC = 4.5 V. Must not be left floating."+        "description": "Channel 1, Input A. Standard high-impedance CMOS input to gate 1; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Must not be left floating."       },       {         "number": "2",         "name": "1B",         "type": "input",-        "description": "Channel 1, Input B. Standard CMOS input to gate 1; combined with 1A to produce 1Y = 1A \u00b7 1B."+        "description": "Channel 1, Input B. Standard CMOS input to gate 1; combined with 1A to produce 1Y = 1A · 1B."       },       {         "number": "3",         "name": "1Y",         "type": "output",-        "description": "Channel 1, Output Y. Balanced CMOS push-pull output; drives \u00b14 mA at VCC = 4.5 V while meeting VOH \u2265 3.84 V / VOL \u2264 0.33 V (-40 \u00b0C to 85 \u00b0C)."+        "description": "Channel 1, Output Y. Balanced CMOS push-pull output; drives ±4 mA at VCC = 4.5 V while meeting VOH ≥ 3.84 V / VOL ≤ 0.33 V (-40 °C to 85 °C)."       },       {         "number": "4",@@ -56,7 +56,7 @@         "number": "5",         "name": "2B",         "type": "input",-        "description": "Channel 2, Input B. Standard CMOS input to gate 2; combined with 2A to produce 2Y = 2A \u00b7 2B."+        "description": "Channel 2, Input B. Standard CMOS input to gate 2; combined with 2A to produce 2Y = 2A · 2B."       },       {         "number": "6",@@ -68,7 +68,7 @@         "number": "7",         "name": "GND",         "type": "power_in",-        "description": "Device ground reference. 0 V return for the logic core and output drivers; continuous current through VCC or GND is limited to \u00b150 mA (absolute max)."+        "description": "Device ground reference. 0 V return for the logic core and output drivers; continuous current through VCC or GND is limited to ±50 mA (absolute max)."       },       {         "number": "8",@@ -86,7 +86,7 @@         "number": "10",         "name": "3B",         "type": "input",-        "description": "Channel 3, Input B. Standard CMOS input to gate 3; combined with 3A to produce 3Y = 3A \u00b7 3B."+        "description": "Channel 3, Input B. Standard CMOS input to gate 3; combined with 3A to produce 3Y = 3A · 3B."       },       {         "number": "11",@@ -104,7 +104,7 @@         "number": "13",         "name": "4B",         "type": "input",-        "description": "Channel 4, Input B. Standard CMOS input to gate 4; combined with 4A to produce 4Y = 4A \u00b7 4B."+        "description": "Channel 4, Input B. Standard CMOS input to gate 4; combined with 4A to produce 4Y = 4A · 4B."       },       {         "number": "14",@@ -174,5 +174,8 @@     "docs/sn74hc08dr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file