SN74HC00

@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sn74hc00",+  "title": "SN74HC00",+  "brief": "TI quad 2-input NAND gate, SOIC-14. HC CMOS, Y = NOT(A AND B), 2-6 V. Datasheet-verified.",   "version": "0.1.0",-  "type": "component",-  "description": "TI quad 2-input NAND gate, SOIC-14. HC CMOS, Y = NOT(A AND B), 2-6 V. Datasheet-verified.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",@@ -11,6 +14,156 @@     "soic-14",     "texas-instruments"   ],+  "component": {+    "mpn": "SN74HC00",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic IC",+    "subcategory": "Quad 2-input NAND gate",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc00.pdf",+    "parts": {+      "symbol": "sn74hc00.kicad_sym",+      "footprint": "sn74hc00.kicad_mod",+      "model_3d": "sn74hc00.glb"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Channel 1, Input A. CMOS logic input to NAND gate 1 (V_IH >= 3.15 V @ Vcc=4.5 V; V_IL <= 1.35 V @ Vcc=4.5 V). Input leakage +/-0.1 uA typ, +/-1000 nA max."+      },+      {+        "number": "2",+        "name": "1B",+        "type": "input",+        "description": "Channel 1, Input B. CMOS logic input to NAND gate 1, paired with 1A."+      },+      {+        "number": "3",+        "name": "1Y",+        "type": "output",+        "description": "Channel 1, Output Y. Push-pull CMOS output equal to NOT(1A AND 1B). Balanced drive of +/-5.2 mA at Vcc = 6 V."+      },+      {+        "number": "4",+        "name": "2A",+        "type": "input",+        "description": "Channel 2, Input A. CMOS logic input to NAND gate 2."+      },+      {+        "number": "5",+        "name": "2B",+        "type": "input",+        "description": "Channel 2, Input B. CMOS logic input to NAND gate 2, paired with 2A."+      },+      {+        "number": "6",+        "name": "2Y",+        "type": "output",+        "description": "Channel 2, Output Y. Push-pull CMOS output equal to NOT(2A AND 2B)."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V). Continuous current through GND limited to +/-50 mA."+      },+      {+        "number": "8",+        "name": "3Y",+        "type": "output",+        "description": "Channel 3, Output Y. Push-pull CMOS output equal to NOT(3A AND 3B)."+      },+      {+        "number": "9",+        "name": "3A",+        "type": "input",+        "description": "Channel 3, Input A. CMOS logic input to NAND gate 3."+      },+      {+        "number": "10",+        "name": "3B",+        "type": "input",+        "description": "Channel 3, Input B. CMOS logic input to NAND gate 3, paired with 3A."+      },+      {+        "number": "11",+        "name": "4Y",+        "type": "output",+        "description": "Channel 4, Output Y. Push-pull CMOS output equal to NOT(4A AND 4B)."+      },+      {+        "number": "12",+        "name": "4A",+        "type": "input",+        "description": "Channel 4, Input A. CMOS logic input to NAND gate 4."+      },+      {+        "number": "13",+        "name": "4B",+        "type": "input",+        "description": "Channel 4, Input B. CMOS logic input to NAND gate 4, paired with 4A."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply. Recommended 2 V to 6 V (5 V nominal); absolute max 7 V. Decouple to GND with a 100 nF ceramic capacitor close to the pin."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74hc00.pdf",+        "pages": 39,+        "sha256": "706cc4f5fd012f08",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Quad 2-input NAND gate",+      "Function": "Y = NOT(A AND B)",+      "Logic family": "HC (high-speed CMOS)",+      "Supply voltage": "2-6 V",+      "Gates": "4 independent",+      "Package": "SOIC-14",+      "Body (L\u00d7W\u00d7H)": "8.65 \u00d7 3.9 \u00d7 1.75 mm"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "sn74hc00",+    "74hc00",+    "quad nand gate",+    "2-input nand logic"+  ],+  "discovery_pitch": "SN74HC00 quad 2-input NAND gate (SOIC-14) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -26,10 +179,5 @@     "docs/sn74hc00-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file