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SN74F573DWR
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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74F573DWR++**Texas Instruments** · Latches · SOIC-20-300mil++SN74F573DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Buffered active-low output enable: when low the eight Q outputs show their normal logic states, and when high they are forced to the high-impedance state without affecting the latch contents. |+| 2 | 1D | input | Data input to latch 1; while LE is high the 1Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 3 | 2D | input | Data input to latch 2; while LE is high the 2Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 4 | 3D | input | Data input to latch 3; while LE is high the 3Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 5 | 4D | input | Data input to latch 4; while LE is high the 4Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 6 | 5D | input | Data input to latch 5; while LE is high the 5Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 7 | 6D | input | Data input to latch 6; while LE is high the 6Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 8 | 7D | input | Data input to latch 7; while LE is high the 7Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 9 | 8D | input | Data input to latch 8; while LE is high the 8Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling). |+| 10 | GND | power_in | Ground reference pin for the device. |+| 11 | LE | input | Latch enable input shared by all eight latches: while high the Q outputs are transparent to D, and taking it low latches the Q outputs (minimum high pulse width 6 ns). |+| 12 | 8Q | tri_state | Latch 8 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 13 | 7Q | tri_state | Latch 7 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 14 | 6Q | tri_state | Latch 6 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 15 | 5Q | tri_state | Latch 5 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 16 | 4Q | tri_state | Latch 4 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 17 | 3Q | tri_state | Latch 3 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 18 | 2Q | tri_state | Latch 2 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 19 | 1Q | tri_state | Latch 1 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA). |+| 20 | VCC | power_in | Positive supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V) for the SN74F573. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74F573DWR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `sn74f573dwr-etched.step` / `sn74f573dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74f573dwr.step` / `sn74f573dwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74f573) (13 pp, sha256 `3e8c5339d5889276`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74f573dwr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74f573dwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74f573dwr.kicad_sym",+ "sn74f573dwr.kicad_mod",+ "sn74f573dwr.glb",+ "sn74f573dwr.step",+ "sn74f573dwr.lbr",+ "docs/hero.png",+ "docs/sn74f573dwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74f573dwr-hero.glb",+ "sn74f573dwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74F573DWR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74f573",+ "parts": {+ "symbol": "sn74f573dwr.kicad_sym",+ "footprint": "sn74f573dwr.kicad_mod",+ "model_3d": "sn74f573dwr-hero.glb",+ "model_3d_plain": "sn74f573dwr.glb",+ "model_3d_step": "sn74f573dwr-etched.step",+ "model_3d_step_plain": "sn74f573dwr.step",+ "lbr": "sn74f573dwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C6804",+ "digikey": "296-14822-2-ND",+ "mouser": "595-SN74F573DWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:56:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-14822-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74F573DWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Buffered active-low output enable: when low the eight Q outputs show their normal logic states, and when high they are forced to the high-impedance state without affecting the latch contents."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Data input to latch 1; while LE is high the 1Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "3",+ "name": "2D",+ "type": "input",+ "description": "Data input to latch 2; while LE is high the 2Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "4",+ "name": "3D",+ "type": "input",+ "description": "Data input to latch 3; while LE is high the 3Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "5",+ "name": "4D",+ "type": "input",+ "description": "Data input to latch 4; while LE is high the 4Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "6",+ "name": "5D",+ "type": "input",+ "description": "Data input to latch 5; while LE is high the 5Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "7",+ "name": "6D",+ "type": "input",+ "description": "Data input to latch 6; while LE is high the 6Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "8",+ "name": "7D",+ "type": "input",+ "description": "Data input to latch 7; while LE is high the 7Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "9",+ "name": "8D",+ "type": "input",+ "description": "Data input to latch 8; while LE is high the 8Q output follows this input, and it is latched when LE goes low (setup 2 ns, hold 3 ns before/after LE falling)."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin for the device."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch enable input shared by all eight latches: while high the Q outputs are transparent to D, and taking it low latches the Q outputs (minimum high pulse width 6 ns)."+ },+ {+ "number": "12",+ "name": "8Q",+ "type": "tri_state",+ "description": "Latch 8 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "13",+ "name": "7Q",+ "type": "tri_state",+ "description": "Latch 7 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "14",+ "name": "6Q",+ "type": "tri_state",+ "description": "Latch 6 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "15",+ "name": "5Q",+ "type": "tri_state",+ "description": "Latch 5 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "16",+ "name": "4Q",+ "type": "tri_state",+ "description": "Latch 4 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "17",+ "name": "3Q",+ "type": "tri_state",+ "description": "Latch 3 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "18",+ "name": "2Q",+ "type": "tri_state",+ "description": "Latch 2 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "19",+ "name": "1Q",+ "type": "tri_state",+ "description": "Latch 1 3-state bus-driving true output, which can be placed in high impedance by OE high and drives highly capacitive or low-impedance loads (IOH max -3 mA, IOL max 24 mA)."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V) for the SN74F573."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout taken from the SN74F573 DW/N TOP VIEW on page 1; the DW (SOIC-20) package applies to SN74F573"+ ],+ "pages_sent": 13,+ "cost_usd": 0.0646,+ "at": "2026-10-08T18:55:15"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74f573",+ "pages": 13,+ "sha256": "3e8c5339d5889276",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74f573dwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74f573dwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8fec916687aef97133384d5b46171eacc714c7283374efcbd2df5ad08a9d8356",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}