component
SN74AUP1G32DCKR
Public Made by Adomby adom
UMW Logic Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+7−4@@ -32,7 +32,7 @@ "number": "1", "name": "A", "type": "input",- "description": "OR gate input A. CMOS logic input, VIH = 0.75*VCC (at 0.8 V) down to 2.0 V (at 3.0-3.6 V VCC). Input leakage \u00b10.1 \u00b5A typ."+ "description": "OR gate input A. CMOS logic input, VIH = 0.75*VCC (at 0.8 V) down to 2.0 V (at 3.0-3.6 V VCC). Input leakage ±0.1 µA typ." }, { "number": "2",@@ -50,13 +50,13 @@ "number": "4", "name": "Y", "type": "output",- "description": "OR gate output, Y = A OR B. Balanced push-pull CMOS output rated \u00b14 mA sink/source; VOH \u2248 VCC-0.1 V at 20 \u00b5A load."+ "description": "OR gate output, Y = A OR B. Balanced push-pull CMOS output rated ±4 mA sink/source; VOH ≈ VCC-0.1 V at 20 µA load." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply, 0.8 V to 3.6 V operating range (absolute max 4.6 V). Quiescent ICC \u2264 0.7 \u00b5A at 3.6 V; bypass with a local 0.1 \u00b5F ceramic to GND."+ "description": "Positive supply, 0.8 V to 3.6 V operating range (absolute max 4.6 V). Quiescent ICC ≤ 0.7 µA at 3.6 V; bypass with a local 0.1 µF ceramic to GND." } ], "provenance": {@@ -130,5 +130,8 @@ "docs/sn74aup1g32dckr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }