SN74AUP1G32DCKR

@@ -0,0 +1,47 @@+# SN74AUP1G32DCKR++**UMW** · Logic Gates · SC-70-5++SN74AUP1G32DCKR from UMW, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | OR gate input A. CMOS logic input, VIH = 0.75*VCC (at 0.8 V) down to 2.0 V (at 3.0-3.6 V VCC). Input leakage ±0.1 µA typ. |+| 2 | B | input | OR gate input B. CMOS logic input, same VIH/VIL thresholds as input A. |+| 3 | GND | power_in | Ground reference (0 V). Return for VCC supply current and logic-low output current. |+| 4 | Y | output | OR gate output, Y = A OR B. Balanced push-pull CMOS output rated ±4 mA sink/source; VOH ≈ VCC-0.1 V at 20 µA load. |+| 5 | VCC | power_in | Positive supply, 0.8 V to 3.6 V operating range (absolute max 4.6 V). Quiescent ICC ≤ 0.7 µA at 3.6 V; bypass with a local 0.1 µF ceramic to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | UMW |+| Package | SC-70-5 |+| Category | Logic |+| Pins | 5 |++## Ordering variants++Same part, different packaging or reel option.++- `SN74AUP1G32DCKR`+- `SN74AUP1G32DCKRDBVR`++## CAD (KiCad official)++- Symbol: `SN74AUP1G32DCKR`+- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`+- 3D model: SC-70-5 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603018419008917504) (9 pp, sha256 `5bb48c257337a5f9`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74aup1g32dckr-datasheet.pdf)

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