component
SN74AUP1G08DBVR
Public Made by Adomby adom
UMW Gates, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -33,6 +33,20 @@ SN74AUP1G08DBVR from UMW, in a SOT-23-5. Pinout and pin descriptions extracted f - Footprint: `Package_TO_SOT_SMD:SOT-23-5` - 3D model: SOT-23-5 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74aup1g08dbvr.step`](sn74aup1g08dbvr.step) | 85 KB | You want the bare part, or you mark your own boards. |+| [`sn74aup1g08dbvr-etched.step`](sn74aup1g08dbvr-etched.step) | 2.6 MB | You want the part with `SN74AUP1G08DBVR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 640 faces against 102 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "sn74aup1g08dbvr",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+9−9@@ -4,7 +4,7 @@ "slug": "sn74aup1g08dbvr", "title": "SN74AUP1G08DBVR", "brief": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,13 +34,13 @@ "number": "1", "name": "A", "type": "input",- "description": "Logic input A of the 2-input AND gate. CMOS input with VIH \u2265 0.75\u00b7VCC and VIL \u2264 0.25\u00b7VCC at VCC = 0.8 V; input voltage range 0 to 3.6 V."+ "description": "Logic input A of the 2-input AND gate. CMOS input with VIH ≥ 0.75·VCC and VIL ≤ 0.25·VCC at VCC = 0.8 V; input voltage range 0 to 3.6 V." }, { "number": "2", "name": "B", "type": "input",- "description": "Logic input B of the 2-input AND gate. CMOS input, same thresholds as pin A; input leakage IIN \u2264 0.2 \u00b5A over 0-3.6 V."+ "description": "Logic input B of the 2-input AND gate. CMOS input, same thresholds as pin A; input leakage IIN ≤ 0.2 µA over 0-3.6 V." }, { "number": "3",@@ -52,13 +52,13 @@ "number": "4", "name": "Y", "type": "output",- "description": "AND-gate output Y = A \u00b7 B. Push-pull CMOS output with balanced 4 mA sink/source capability; VOH \u2248 VCC\u22120.1 V at \u00b120 \u00b5A load."+ "description": "AND-gate output Y = A · B. Push-pull CMOS output with balanced 4 mA sink/source capability; VOH ≈ VCC−0.1 V at ±20 µA load." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply. Recommended operating range 0.8 V to 3.6 V; absolute max \u22120.5 V to 4.6 V. Quiescent ICC \u2264 0.7 \u00b5A at VCC = 3.6 V. Bypass with a local 0.1 \u00b5F ceramic to GND."+ "description": "Positive supply. Recommended operating range 0.8 V to 3.6 V; absolute max −0.5 V to 4.6 V. Quiescent ICC ≤ 0.7 µA at VCC = 3.6 V. Bypass with a local 0.1 µF ceramic to GND." } ], "provenance": {@@ -132,9 +132,9 @@ "docs/hero.png", "docs/sn74aup1g08dbvr-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D." }