SN74AUP1G08DBVR

@@ -0,0 +1,44 @@+# SN74AUP1G08DBVR++**UMW** · Gates · SOT-23-5++SN74AUP1G08DBVR from UMW, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Logic input A of the 2-input AND gate. CMOS input with VIH ≥ 0.75·VCC and VIL ≤ 0.25·VCC at VCC = 0.8 V; input voltage range 0 to 3.6 V. |+| 2 | B | input | Logic input B of the 2-input AND gate. CMOS input, same thresholds as pin A; input leakage IIN ≤ 0.2 µA over 0-3.6 V. |+| 3 | GND | power_in | Ground reference (0 V). Common return for supply and I/O. |+| 4 | Y | output | AND-gate output Y = A · B. Push-pull CMOS output with balanced 4 mA sink/source capability; VOH ≈ VCC−0.1 V at ±20 µA load. |+| 5 | VCC | power_in | Positive supply. Recommended operating range 0.8 V to 3.6 V; absolute max −0.5 V to 4.6 V. Quiescent ICC ≤ 0.7 µA at VCC = 3.6 V. Bypass with a local 0.1 µF ceramic to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | UMW |+| Package | SOT-23-5 |+| Category | Logic |+| Pins | 5 |++## Ordering variants++- `SN74AUP1G08DBVRDBVR`++## CAD (KiCad official)++- Symbol: `SN74AUP1G08DBVR`+- Footprint: `Package_TO_SOT_SMD:SOT-23-5`+- 3D model: SOT-23-5 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [UMW datasheet](docs/sn74aup1g08dbvr-datasheet.pdf) (15 pp, sha256 `458a5f38e27bdcad`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74aup1g08dbvr-datasheet.pdf)

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