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SN74ALVCH16841DLR
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Texas Instruments Latches, SSOP-56-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+92@@ -0,0 +1,92 @@+# SN74ALVCH16841DLR++**Texas Instruments** · Latches · SSOP-56-300mil++SN74ALVCH16841DLR from Texas Instruments, in a SSOP-56-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1OE | input | Active-low buffered output enable for the 1Q outputs; a high level places outputs 1Q1 to 1Q10 in the high-impedance state and does not affect latch operation. |+| 2 | 1Q1 | tri_state | 3-state true data output of latch 1, bit 1; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 3 | 1Q2 | tri_state | 3-state true data output of latch 1, bit 2; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 4 | GND | power_in | Ground reference. |+| 5 | 1Q3 | tri_state | 3-state true data output of latch 1, bit 3; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 6 | 1Q4 | tri_state | 3-state true data output of latch 1, bit 4; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 7 | VCC | power_in | Supply voltage; 1.65 V to 3.6 V recommended operating range. |+| 8 | 1Q5 | tri_state | 3-state true data output of latch 1, bit 5; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 9 | 1Q6 | tri_state | 3-state true data output of latch 1, bit 6; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 10 | 1Q7 | tri_state | 3-state true data output of latch 1, bit 7; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 11 | GND | power_in | Ground reference. |+| 12 | 1Q8 | tri_state | 3-state true data output of latch 1, bit 8; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 13 | 1Q9 | tri_state | 3-state true data output of latch 1, bit 9; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 14 | 1Q10 | tri_state | 3-state true data output of latch 1, bit 10; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 15 | 2Q1 | tri_state | 3-state true data output of latch 2, bit 1; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 16 | 2Q2 | tri_state | 3-state true data output of latch 2, bit 2; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 17 | 2Q3 | tri_state | 3-state true data output of latch 2, bit 3; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 18 | GND | power_in | Ground reference. |+| 19 | 2Q4 | tri_state | 3-state true data output of latch 2, bit 4; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 20 | 2Q5 | tri_state | 3-state true data output of latch 2, bit 5; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 21 | 2Q6 | tri_state | 3-state true data output of latch 2, bit 6; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 22 | VCC | power_in | Supply voltage; 1.65 V to 3.6 V recommended operating range. |+| 23 | 2Q7 | tri_state | 3-state true data output of latch 2, bit 7; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 24 | 2Q8 | tri_state | 3-state true data output of latch 2, bit 8; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 25 | GND | power_in | Ground reference. |+| 26 | 2Q9 | tri_state | 3-state true data output of latch 2, bit 9; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 27 | 2Q10 | tri_state | 3-state true data output of latch 2, bit 10; rated IOH -24 mA and IOL 24 mA at VCC = 3 V. |+| 28 | 2OE | input | Active-low buffered output enable for the 2Q outputs; a high level places outputs 2Q1 to 2Q10 in the high-impedance state and does not affect latch operation. |+| 29 | 2LE | input | Latch enable for latch group 2; Q outputs follow D while high and are latched when taken low. |+| 30 | 2D10 | input | Noninverting data input of latch 2, bit 10, with active bus hold; input must remain between 0 V and VCC. |+| 31 | 2D9 | input | Noninverting data input of latch 2, bit 9, with active bus hold; input must remain between 0 V and VCC. |+| 32 | GND | power_in | Ground reference. |+| 33 | 2D8 | input | Noninverting data input of latch 2, bit 8, with active bus hold; input must remain between 0 V and VCC. |+| 34 | 2D7 | input | Noninverting data input of latch 2, bit 7, with active bus hold; input must remain between 0 V and VCC. |+| 35 | VCC | power_in | Supply voltage; 1.65 V to 3.6 V recommended operating range. |+| 36 | 2D6 | input | Noninverting data input of latch 2, bit 6, with active bus hold; input must remain between 0 V and VCC. |+| 37 | 2D5 | input | Noninverting data input of latch 2, bit 5, with active bus hold; input must remain between 0 V and VCC. |+| 38 | 2D4 | input | Noninverting data input of latch 2, bit 4, with active bus hold; input must remain between 0 V and VCC. |+| 39 | GND | power_in | Ground reference. |+| 40 | 2D3 | input | Noninverting data input of latch 2, bit 3, with active bus hold; input must remain between 0 V and VCC. |+| 41 | 2D2 | input | Noninverting data input of latch 2, bit 2, with active bus hold; input must remain between 0 V and VCC. |+| 42 | 2D1 | input | Noninverting data input of latch 2, bit 1, with active bus hold; input must remain between 0 V and VCC. |+| 43 | 1D10 | input | Noninverting data input of latch 1, bit 10, with active bus hold; input must remain between 0 V and VCC. |+| 44 | 1D9 | input | Noninverting data input of latch 1, bit 9, with active bus hold; input must remain between 0 V and VCC. |+| 45 | 1D8 | input | Noninverting data input of latch 1, bit 8, with active bus hold; input must remain between 0 V and VCC. |+| 46 | GND | power_in | Ground reference. |+| 47 | 1D7 | input | Noninverting data input of latch 1, bit 7, with active bus hold; input must remain between 0 V and VCC. |+| 48 | 1D6 | input | Noninverting data input of latch 1, bit 6, with active bus hold; input must remain between 0 V and VCC. |+| 49 | 1D5 | input | Noninverting data input of latch 1, bit 5, with active bus hold; input must remain between 0 V and VCC. |+| 50 | VCC | power_in | Supply voltage; 1.65 V to 3.6 V recommended operating range. |+| 51 | 1D4 | input | Noninverting data input of latch 1, bit 4, with active bus hold; input must remain between 0 V and VCC. |+| 52 | 1D3 | input | Noninverting data input of latch 1, bit 3, with active bus hold; input must remain between 0 V and VCC. |+| 53 | GND | power_in | Ground reference. |+| 54 | 1D2 | input | Noninverting data input of latch 1, bit 2, with active bus hold; input must remain between 0 V and VCC. |+| 55 | 1D1 | input | Noninverting data input of latch 1, bit 1, with active bus hold; input must remain between 0 V and VCC. |+| 56 | 1LE | input | Latch enable for latch group 1; Q outputs follow D while high and are latched when taken low. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SSOP-56-300mil |+| Category | Logic |+| Pins | 56 |++## CAD (KiCad official)++- Symbol: `SN74ALVCH16841DLR`+- Footprint: `Package_SO:SSOP-56_7.5x18.5mm_P0.635mm`+- 3D model: SSOP-56-300mil (KiCad packages3D, STEP)+- 3D model files: `sn74alvch16841dlr-etched.step` / `sn74alvch16841dlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74alvch16841dlr.step` / `sn74alvch16841dlr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74alvch16841) (19 pp, sha256 `0ca1eefeed0667c3`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74alvch16841dlr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74alvch16841dlr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74alvch16841dlr.kicad_sym",+ "sn74alvch16841dlr.kicad_mod",+ "sn74alvch16841dlr.glb",+ "sn74alvch16841dlr.step",+ "sn74alvch16841dlr.lbr",+ "docs/hero.png",+ "docs/sn74alvch16841dlr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74alvch16841dlr-hero.glb",+ "sn74alvch16841dlr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74ALVCH16841DLR",+ "manufacturer": "Texas Instruments",+ "package": "SSOP-56-300mil",+ "pin_count": 56,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74alvch16841",+ "parts": {+ "symbol": "sn74alvch16841dlr.kicad_sym",+ "footprint": "sn74alvch16841dlr.kicad_mod",+ "model_3d": "sn74alvch16841dlr-hero.glb",+ "model_3d_plain": "sn74alvch16841dlr.glb",+ "model_3d_step": "sn74alvch16841dlr-etched.step",+ "model_3d_step_plain": "sn74alvch16841dlr.step",+ "lbr": "sn74alvch16841dlr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2675502",+ "digikey": "296-SN74ALVCH16841DLRTR-ND",+ "mouser": "595-74ALVCH16841DLR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T22:28:26Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-SN74ALVCH16841DLRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-74ALVCH16841DLR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1OE",+ "type": "input",+ "description": "Active-low buffered output enable for the 1Q outputs; a high level places outputs 1Q1 to 1Q10 in the high-impedance state and does not affect latch operation."+ },+ {+ "number": "2",+ "name": "1Q1",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 1; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "3",+ "name": "1Q2",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 2; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "5",+ "name": "1Q3",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 3; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "6",+ "name": "1Q4",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 4; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "7",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; 1.65 V to 3.6 V recommended operating range."+ },+ {+ "number": "8",+ "name": "1Q5",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 5; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "9",+ "name": "1Q6",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 6; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "10",+ "name": "1Q7",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 7; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "11",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "12",+ "name": "1Q8",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 8; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "13",+ "name": "1Q9",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 9; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "14",+ "name": "1Q10",+ "type": "tri_state",+ "description": "3-state true data output of latch 1, bit 10; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "15",+ "name": "2Q1",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 1; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "16",+ "name": "2Q2",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 2; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "17",+ "name": "2Q3",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 3; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "19",+ "name": "2Q4",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 4; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "20",+ "name": "2Q5",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 5; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "21",+ "name": "2Q6",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 6; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "22",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; 1.65 V to 3.6 V recommended operating range."+ },+ {+ "number": "23",+ "name": "2Q7",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 7; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "24",+ "name": "2Q8",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 8; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "25",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "26",+ "name": "2Q9",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 9; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "27",+ "name": "2Q10",+ "type": "tri_state",+ "description": "3-state true data output of latch 2, bit 10; rated IOH -24 mA and IOL 24 mA at VCC = 3 V."+ },+ {+ "number": "28",+ "name": "2OE",+ "type": "input",+ "description": "Active-low buffered output enable for the 2Q outputs; a high level places outputs 2Q1 to 2Q10 in the high-impedance state and does not affect latch operation."+ },+ {+ "number": "29",+ "name": "2LE",+ "type": "input",+ "description": "Latch enable for latch group 2; Q outputs follow D while high and are latched when taken low."+ },+ {+ "number": "30",+ "name": "2D10",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 10, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "31",+ "name": "2D9",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 9, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "32",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "33",+ "name": "2D8",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 8, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "34",+ "name": "2D7",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 7, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "35",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; 1.65 V to 3.6 V recommended operating range."+ },+ {+ "number": "36",+ "name": "2D6",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 6, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "37",+ "name": "2D5",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 5, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "38",+ "name": "2D4",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 4, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "39",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "40",+ "name": "2D3",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 3, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "41",+ "name": "2D2",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 2, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "42",+ "name": "2D1",+ "type": "input",+ "description": "Noninverting data input of latch 2, bit 1, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "43",+ "name": "1D10",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 10, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "44",+ "name": "1D9",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 9, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "45",+ "name": "1D8",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 8, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "46",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "47",+ "name": "1D7",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 7, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "48",+ "name": "1D6",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 6, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "49",+ "name": "1D5",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 5, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "50",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; 1.65 V to 3.6 V recommended operating range."+ },+ {+ "number": "51",+ "name": "1D4",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 4, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "52",+ "name": "1D3",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 3, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "53",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference."+ },+ {+ "number": "54",+ "name": "1D2",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 2, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "55",+ "name": "1D1",+ "type": "input",+ "description": "Noninverting data input of latch 1, bit 1, with active bus hold; input must remain between 0 V and VCC."+ },+ {+ "number": "56",+ "name": "1LE",+ "type": "input",+ "description": "Latch enable for latch group 1; Q outputs follow D while high and are latched when taken low."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The DL pin diagram is extracted as separate column text, so pin-to-name mapping was reconstructed by; The datasheet covers DGG (TSSOP) and DL (SSOP) packages with one shared pin diagram; the DL pinout i; Pin types and descriptions for OE, LE, D and Q pins are classified from the function table and logic"+ ],+ "pages_sent": 19,+ "cost_usd": 0.1084,+ "at": "2026-10-07T22:27:59"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74alvch16841",+ "pages": 19,+ "sha256": "0ca1eefeed0667c3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 56,+ "described": 56,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74alvch16841dlr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.35,+ 18.5,+ 2.99+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "496b138c9bddb6111fccc97928b5e654846ac39b68862745293b24c720d158e5",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74alvch16841dlr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.35,+ 18.5,+ 2.99+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "93c96899ff822dbe96b2a31345918b572239a36cd9f90b2fefe50d71b96f1ee4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}