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SN74ALS873BDWR
Public Made by Adomby adom
Texas Instruments Latches, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# SN74ALS873BDWR++**Texas Instruments** · Latches · SOIC-24-300mil++SN74ALS873BDWR from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLR | input | Active-low clear for latch group 1; when low, the 1Q outputs go low independently of 1LE. |+| 2 | 1OE | input | Output enable for latch group 1; when at a high logic level, the 1Q outputs are forced to the high-impedance state. |+| 3 | 1D1 | input | Data input for bit 1 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns). |+| 4 | 1D2 | input | Data input for bit 2 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns). |+| 5 | 1D3 | input | Data input for bit 3 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns). |+| 6 | 1D4 | input | Data input for bit 4 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns). |+| 7 | 2D1 | input | Data input for bit 1 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns). |+| 8 | 2D2 | input | Data input for bit 2 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns). |+| 9 | 2D3 | input | Data input for bit 3 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns). |+| 10 | 2D4 | input | Data input for bit 4 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns). |+| 11 | 2OE | input | Output enable for latch group 2; when at a high logic level, the 2Q outputs are forced to the high-impedance state. |+| 12 | GND | power_in | Ground reference pin for the device. |+| 13 | 2CLR | input | Active-low clear for latch group 2; when low, the 2Q outputs go low independently of 2LE. |+| 14 | 2LE | input | Latch enable for group 2; while high the 2Q outputs follow the D inputs, and when low the outputs are latched. |+| 15 | 2Q4 | tri_state | Bit 4 3-state buffer output of latch group 2, designed to drive bus lines directly. |+| 16 | 2Q3 | tri_state | Bit 3 3-state buffer output of latch group 2, designed to drive bus lines directly. |+| 17 | 2Q2 | tri_state | Bit 2 3-state buffer output of latch group 2, designed to drive bus lines directly. |+| 18 | 2Q1 | tri_state | Bit 1 3-state buffer output of latch group 2, designed to drive bus lines directly. |+| 19 | 1Q4 | tri_state | Bit 4 3-state buffer output of latch group 1, designed to drive bus lines directly. |+| 20 | 1Q3 | tri_state | Bit 3 3-state buffer output of latch group 1, designed to drive bus lines directly. |+| 21 | 1Q2 | tri_state | Bit 2 3-state buffer output of latch group 1, designed to drive bus lines directly. |+| 22 | 1Q1 | tri_state | Bit 1 3-state buffer output of latch group 1, designed to drive bus lines directly. |+| 23 | 1LE | input | Latch enable for group 1; while high the 1Q outputs follow the D inputs, and when low the outputs are latched. |+| 24 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V with 5 V nominal (absolute maximum 7 V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-24-300mil |+| Category | Logic |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `SN74ALS873BDWR`+- Footprint: `Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm`+- 3D model: SOIC-24-300mil (KiCad packages3D, STEP)+- 3D model files: `sn74als873bdwr-etched.step` / `sn74als873bdwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74als873bdwr.step` / `sn74als873bdwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn54als873b) (15 pp, sha256 `7a37dd6b1e3368fa`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74als873bdwr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74als873bdwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74als873bdwr.kicad_sym",+ "sn74als873bdwr.kicad_mod",+ "sn74als873bdwr.glb",+ "sn74als873bdwr.step",+ "sn74als873bdwr.lbr",+ "docs/hero.png",+ "docs/sn74als873bdwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74als873bdwr-hero.glb",+ "sn74als873bdwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74ALS873BDWR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-24-300mil",+ "pin_count": 24,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn54als873b",+ "parts": {+ "symbol": "sn74als873bdwr.kicad_sym",+ "footprint": "sn74als873bdwr.kicad_mod",+ "model_3d": "sn74als873bdwr-hero.glb",+ "model_3d_plain": "sn74als873bdwr.glb",+ "model_3d_step": "sn74als873bdwr-etched.step",+ "model_3d_step_plain": "sn74als873bdwr.step",+ "lbr": "sn74als873bdwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2675408",+ "digikey": "296-29550-2-ND",+ "mouser": "595-SN74ALS873BDWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:07:16Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-29550-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74ALS873BDWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1CLR",+ "type": "input",+ "description": "Active-low clear for latch group 1; when low, the 1Q outputs go low independently of 1LE."+ },+ {+ "number": "2",+ "name": "1OE",+ "type": "input",+ "description": "Output enable for latch group 1; when at a high logic level, the 1Q outputs are forced to the high-impedance state."+ },+ {+ "number": "3",+ "name": "1D1",+ "type": "input",+ "description": "Data input for bit 1 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "4",+ "name": "1D2",+ "type": "input",+ "description": "Data input for bit 2 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "5",+ "name": "1D3",+ "type": "input",+ "description": "Data input for bit 3 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "6",+ "name": "1D4",+ "type": "input",+ "description": "Data input for bit 4 of latch group 1; while 1LE is high the 1Q output follows this input, and it is latched when 1LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "7",+ "name": "2D1",+ "type": "input",+ "description": "Data input for bit 1 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "8",+ "name": "2D2",+ "type": "input",+ "description": "Data input for bit 2 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "9",+ "name": "2D3",+ "type": "input",+ "description": "Data input for bit 3 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "10",+ "name": "2D4",+ "type": "input",+ "description": "Data input for bit 4 of latch group 2; while 2LE is high the 2Q output follows this input, and it is latched when 2LE goes low (setup 10 ns, hold 7 ns)."+ },+ {+ "number": "11",+ "name": "2OE",+ "type": "input",+ "description": "Output enable for latch group 2; when at a high logic level, the 2Q outputs are forced to the high-impedance state."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin for the device."+ },+ {+ "number": "13",+ "name": "2CLR",+ "type": "input",+ "description": "Active-low clear for latch group 2; when low, the 2Q outputs go low independently of 2LE."+ },+ {+ "number": "14",+ "name": "2LE",+ "type": "input",+ "description": "Latch enable for group 2; while high the 2Q outputs follow the D inputs, and when low the outputs are latched."+ },+ {+ "number": "15",+ "name": "2Q4",+ "type": "tri_state",+ "description": "Bit 4 3-state buffer output of latch group 2, designed to drive bus lines directly."+ },+ {+ "number": "16",+ "name": "2Q3",+ "type": "tri_state",+ "description": "Bit 3 3-state buffer output of latch group 2, designed to drive bus lines directly."+ },+ {+ "number": "17",+ "name": "2Q2",+ "type": "tri_state",+ "description": "Bit 2 3-state buffer output of latch group 2, designed to drive bus lines directly."+ },+ {+ "number": "18",+ "name": "2Q1",+ "type": "tri_state",+ "description": "Bit 1 3-state buffer output of latch group 2, designed to drive bus lines directly."+ },+ {+ "number": "19",+ "name": "1Q4",+ "type": "tri_state",+ "description": "Bit 4 3-state buffer output of latch group 1, designed to drive bus lines directly."+ },+ {+ "number": "20",+ "name": "1Q3",+ "type": "tri_state",+ "description": "Bit 3 3-state buffer output of latch group 1, designed to drive bus lines directly."+ },+ {+ "number": "21",+ "name": "1Q2",+ "type": "tri_state",+ "description": "Bit 2 3-state buffer output of latch group 1, designed to drive bus lines directly."+ },+ {+ "number": "22",+ "name": "1Q1",+ "type": "tri_state",+ "description": "Bit 1 3-state buffer output of latch group 1, designed to drive bus lines directly."+ },+ {+ "number": "23",+ "name": "1LE",+ "type": "input",+ "description": "Latch enable for group 1; while high the 1Q outputs follow the D inputs, and when low the outputs are latched."+ },+ {+ "number": "24",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended 4.5 V to 5.5 V with 5 V nominal (absolute maximum 7 V)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers are taken from the logic symbol annotations on page 2 (\"Pin numbers shown are for the DW; The datasheet lists the SN74ALS873B DW package as 24-pin SOIC; the package addendum (page 8) confirm; Ground and clear/enable descriptions are limited to what the datasheet states; the datasheet gives n"+ ],+ "pages_sent": 15,+ "cost_usd": 0.0817,+ "at": "2026-10-08T16:06:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn54als873b",+ "pages": 15,+ "sha256": "7a37dd6b1e3368fa",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74als873bdwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 15.4,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4b0d20f82f5b0124fecfe11c941274a3c865a30f7baee8b8fadd7df55972d4cd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74als873bdwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 15.4,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "299156769cbc0cef366b2931d78d12a7940dacfb5db3d41a847faac0c2ef3c72",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}