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SN74ALS259DR
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Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN74ALS259DR++**Texas Instruments** · Latches · SOIC-16++SN74ALS259DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | S0 | input | Address select input S0 (LSB) chooses which of the eight latches is addressed, and it must be stable with 15 ns minimum setup before G rises and 0 ns hold after G rises for the SN74ALS259. |+| 2 | S1 | input | Address select input S1 chooses which of the eight latches is addressed, and it must be stable with 15 ns minimum setup before G rises and 0 ns hold after G rises for the SN74ALS259. |+| 3 | S2 | input | Address select input S2 (MSB) chooses which of the eight latches is addressed, and it must be stable with 15 ns minimum setup before G rises and 0 ns hold after G rises for the SN74ALS259. |+| 4 | Q0 | output | Latch output Q0 follows D when latch 0 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 5 | Q1 | output | Latch output Q1 follows D when latch 1 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 6 | Q2 | output | Latch output Q2 follows D when latch 2 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 7 | Q3 | output | Latch output Q3 follows D when latch 3 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 8 | GND | power_in | Ground reference for the device. |+| 9 | Q4 | output | Latch output Q4 follows D when latch 4 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 10 | Q5 | output | Latch output Q5 follows D when latch 5 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 11 | Q6 | output | Latch output Q6 follows D when latch 6 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 12 | Q7 | output | Latch output Q7 follows D when latch 7 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA. |+| 13 | D | input | Data input written into the addressed latch when G is low and CLR is high, with 15 ns minimum setup and 0 ns hold relative to G rising for the SN74ALS259. |+| 14 | G | input | Active-low enable G: the addressed latch takes the D level while G is low, and G should be held high while the address lines change to avoid erroneous data entry. |+| 15 | CLR | input | Active-low asynchronous clear: when low, all outputs Q0 through Q7 are forced low regardless of address and data, with a minimum low pulse of 10 ns. |+| 16 | VCC | power_in | Supply voltage, recommended 4.5 V to 5.5 V (5 V nominal), with an absolute maximum of 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN74ALS259DR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `sn74als259dr-etched.step` / `sn74als259dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74als259dr.step` / `sn74als259dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74als259.pdf) (15 pp, sha256 `cce17731d8cdfeff`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74als259dr-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "sn74als259dr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74als259dr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74als259dr.kicad_sym",+ "sn74als259dr.kicad_mod",+ "sn74als259dr.glb",+ "sn74als259dr.step",+ "sn74als259dr.lbr",+ "docs/hero.png",+ "docs/sn74als259dr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74als259dr-hero.glb",+ "sn74als259dr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74ALS259DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74als259.pdf",+ "parts": {+ "symbol": "sn74als259dr.kicad_sym",+ "footprint": "sn74als259dr.kicad_mod",+ "model_3d": "sn74als259dr-hero.glb",+ "model_3d_plain": "sn74als259dr.glb",+ "model_3d_step": "sn74als259dr-etched.step",+ "model_3d_step_plain": "sn74als259dr.step",+ "lbr": "sn74als259dr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2871340",+ "digikey": "296-14729-2-ND",+ "mouser": "595-SN74ALS259DR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T22:48:53Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-14729-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74ALS259DR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "S0",+ "type": "input",+ "description": "Address select input S0 (LSB) chooses which of the eight latches is addressed, and it must be stable with 15 ns minimum setup before G rises and 0 ns hold after G rises for the SN74ALS259."+ },+ {+ "number": "2",+ "name": "S1",+ "type": "input",+ "description": "Address select input S1 chooses which of the eight latches is addressed, and it must be stable with 15 ns minimum setup before G rises and 0 ns hold after G rises for the SN74ALS259."+ },+ {+ "number": "3",+ "name": "S2",+ "type": "input",+ "description": "Address select input S2 (MSB) chooses which of the eight latches is addressed, and it must be stable with 15 ns minimum setup before G rises and 0 ns hold after G rises for the SN74ALS259."+ },+ {+ "number": "4",+ "name": "Q0",+ "type": "output",+ "description": "Latch output Q0 follows D when latch 0 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "5",+ "name": "Q1",+ "type": "output",+ "description": "Latch output Q1 follows D when latch 1 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "6",+ "name": "Q2",+ "type": "output",+ "description": "Latch output Q2 follows D when latch 2 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "7",+ "name": "Q3",+ "type": "output",+ "description": "Latch output Q3 follows D when latch 3 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "9",+ "name": "Q4",+ "type": "output",+ "description": "Latch output Q4 follows D when latch 4 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "10",+ "name": "Q5",+ "type": "output",+ "description": "Latch output Q5 follows D when latch 5 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "11",+ "name": "Q6",+ "type": "output",+ "description": "Latch output Q6 follows D when latch 6 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "12",+ "name": "Q7",+ "type": "output",+ "description": "Latch output Q7 follows D when latch 7 is addressed in the addressable-latch mode, and is rated for IOL of 8 mA and IOH of −0.4 mA."+ },+ {+ "number": "13",+ "name": "D",+ "type": "input",+ "description": "Data input written into the addressed latch when G is low and CLR is high, with 15 ns minimum setup and 0 ns hold relative to G rising for the SN74ALS259."+ },+ {+ "number": "14",+ "name": "G",+ "type": "input",+ "description": "Active-low enable G: the addressed latch takes the D level while G is low, and G should be held high while the address lines change to avoid erroneous data entry."+ },+ {+ "number": "15",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear: when low, all outputs Q0 through Q7 are forced low regardless of address and data, with a minimum low pulse of 10 ns."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended 4.5 V to 5.5 V (5 V nominal), with an absolute maximum of 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin-table text in the extracted datasheet is garbled. The pin assignments were reconstructed fro; The datasheet gives the pinout for the D, J and N packages. The SN74ALS259DR is the SOIC (D) 16-pin "+ ],+ "pages_sent": 15,+ "cost_usd": 0.0656,+ "at": "2026-10-07T22:48:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74als259.pdf",+ "pages": 15,+ "sha256": "cce17731d8cdfeff",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74als259dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74als259dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2fc843e4b552fed89c16dd5d124b0a30672300f2617a1d35e10632308fd71de",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}