SN74AHCT1G00DBVR - Commit

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Ray ·2e9cb4261c ·1mo ago ·parent 3d50ed0
1 file changed +8−5
page.json+8−5
@@ -32,13 +32,13 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A of the 2-input NAND gate. TTL-voltage compatible: VIH = 2 V min, VIL = 0.8 V max at VCC = 4.5-5.5 V. Input current \u00b11 \u00b5A max; must not be left floating (tie to VCC or GND when unused)."+        "description": "Logic input A of the 2-input NAND gate. TTL-voltage compatible: VIH = 2 V min, VIL = 0.8 V max at VCC = 4.5-5.5 V. Input current ±1 µA max; must not be left floating (tie to VCC or GND when unused)."       },       {         "number": "2",         "name": "B",         "type": "input",-        "description": "Logic input B of the 2-input NAND gate. TTL-voltage compatible: VIH = 2 V min, VIL = 0.8 V max at VCC = 4.5-5.5 V. Input current \u00b11 \u00b5A max; must not be left floating (tie to VCC or GND when unused)."+        "description": "Logic input B of the 2-input NAND gate. TTL-voltage compatible: VIH = 2 V min, VIL = 0.8 V max at VCC = 4.5-5.5 V. Input current ±1 µA max; must not be left floating (tie to VCC or GND when unused)."       },       {         "number": "3",@@ -50,13 +50,13 @@         "number": "4",         "name": "Y",         "type": "output",-        "description": "NAND gate output, Y = NOT(A AND B). Push-pull CMOS output with \u00b18 mA drive at VCC = 5 V (IOH = -8 mA, IOL = 8 mA)."+        "description": "NAND gate output, Y = NOT(A AND B). Push-pull CMOS output with ±8 mA drive at VCC = 5 V (IOH = -8 mA, IOL = 8 mA)."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply voltage pin. Recommended operating range 4.5 V to 5.5 V. Quiescent supply current ICC = 10 \u00b5A max. Bypass with a local ceramic capacitor to GND."+        "description": "Positive supply voltage pin. Recommended operating range 4.5 V to 5.5 V. Quiescent supply current ICC = 10 µA max. Bypass with a local ceramic capacitor to GND."       }     ],     "provenance": {@@ -120,5 +120,8 @@     "docs/sn74ahct1g00dbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file