SN74AHC1G00DCKR

@@ -0,0 +1,48 @@+# SN74AHC1G00DCKR++**Texas Instruments** · Gates · SC-70-5++SN74AHC1G00DCKR from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | NAND gate logic input A. CMOS Schmitt-trigger input, overvoltage tolerant to 5.5 V regardless of VCC. Unused inputs must be tied to VCC or GND. |+| 2 | B | input | NAND gate logic input B. CMOS Schmitt-trigger input, overvoltage tolerant to 5.5 V regardless of VCC. Unused inputs must be tied to VCC or GND. |+| 3 | GND | power_in | Ground reference (0 V) for the device. |+| 4 | Y | output | NAND gate output, Y = NOT(A AND B). Totem-pole CMOS output rated for +/-8 mA drive at VCC = 5 V (+/-4 mA at 3.3 V). Load current must not exceed 25 mA per output and 50 mA total for the part; do not pull above VCC. |+| 5 | VCC | power_in | Positive supply, 2 V to 5.5 V recommended (absolute max 7 V). Bypass locally with a 0.1 uF ceramic capacitor to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SC-70-5 |+| Category | Logic |+| Pins | 5 |++## Ordering variants++- `SN74AHC1G00DCKRDCKR`+- `SN74AHC1G00DCKRDCKT`+- `SN74AHC1G00DCKRDBVR`+- `SN74AHC1G00DCKRDBVT`+- `SN74AHC1G00DCKRDRLR`++## CAD (KiCad official)++- Symbol: `SN74AHC1G00DCKR`+- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`+- 3D model: SC-70-5 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahc1g00.pdf) (28 pp, sha256 `a36352df5fcce3eb`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ahc1g00dckr-datasheet.pdf)

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