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SN74ACT533PWR
Public Made by Adomby adom
Texas Instruments Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74ACT533PWR++**Texas Instruments** · Latches · TSSOP-20++SN74ACT533PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Active-low buffered output enable that places all eight Q outputs in the high-impedance state when high; it should be tied to VCC through a pullup resistor to keep the outputs high-impedance during power up or power down. |+| 2 | 1Q | tri_state | Inverting 3-state output of latch 1 that follows the complement of 1D while LE is high and is high-impedance when OE is high. |+| 3 | 1D | input | Data input to latch 1; it must be set up at least 4 ns (min, SN74ACT533 at 4.5-5.5 V) before LE falls and held at least 2.5 ns after LE falls. |+| 4 | 2D | input | Data input to latch 2; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 5 | 2Q | tri_state | Inverting 3-state output of latch 2 that follows the complement of 2D while LE is high and is high-impedance when OE is high. |+| 6 | 3Q | tri_state | Inverting 3-state output of latch 3 that follows the complement of 3D while LE is high and is high-impedance when OE is high. |+| 7 | 3D | input | Data input to latch 3; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 8 | 4D | input | Data input to latch 4; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 9 | 4Q | tri_state | Inverting 3-state output of latch 4 that follows the complement of 4D while LE is high and is high-impedance when OE is high. |+| 10 | GND | power_in | Ground reference; the datasheet requires all unused inputs to be held at VCC or GND for proper operation. |+| 11 | LE | input | Latch enable: when high the Q outputs follow the complement of D, and when taken low the outputs latch; the minimum LE high pulse width is 6 ns for SN74ACT533. |+| 12 | 5Q | tri_state | Inverting 3-state output of latch 5 that follows the complement of 5D while LE is high and is high-impedance when OE is high. |+| 13 | 5D | input | Data input to latch 5; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 14 | 6D | input | Data input to latch 6; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 15 | 6Q | tri_state | Inverting 3-state output of latch 6 that follows the complement of 6D while LE is high and is high-impedance when OE is high. |+| 16 | 7Q | tri_state | Inverting 3-state output of latch 7 that follows the complement of 7D while LE is high and is high-impedance when OE is high. |+| 17 | 7D | input | Data input to latch 7; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 18 | 8D | input | Data input to latch 8; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls. |+| 19 | 8Q | tri_state | Inverting 3-state output of latch 8 that follows the complement of 8D while LE is high and is high-impedance when OE is high. |+| 20 | VCC | power_in | Supply voltage; the recommended operating range is 4.5 V to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74ACT533PWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `sn74act533pwr-etched.step` / `sn74act533pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act533pwr.step` / `sn74act533pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74act533.pdf) (11 pp, sha256 `3b8982b6e118ce9b`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74act533pwr-datasheet.pdf)
page.jsonadded+272@@ -0,0 +1,272 @@+{+ "slug": "sn74act533pwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74act533pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74act533pwr.kicad_sym",+ "sn74act533pwr.kicad_mod",+ "sn74act533pwr.glb",+ "sn74act533pwr.step",+ "sn74act533pwr.lbr",+ "docs/hero.png",+ "docs/sn74act533pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74act533pwr-hero.glb",+ "sn74act533pwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74ACT533PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74act533.pdf",+ "parts": {+ "symbol": "sn74act533pwr.kicad_sym",+ "footprint": "sn74act533pwr.kicad_mod",+ "model_3d": "sn74act533pwr-hero.glb",+ "model_3d_plain": "sn74act533pwr.glb",+ "model_3d_step": "sn74act533pwr-etched.step",+ "model_3d_step_plain": "sn74act533pwr.step",+ "lbr": "sn74act533pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2869027",+ "digikey": "296-4427-2-ND",+ "mouser": "595-SN74ACT533PWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:50:25Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-4427-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74ACT533PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Active-low buffered output enable that places all eight Q outputs in the high-impedance state when high; it should be tied to VCC through a pullup resistor to keep the outputs high-impedance during power up or power down."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 1 that follows the complement of 1D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Data input to latch 1; it must be set up at least 4 ns (min, SN74ACT533 at 4.5-5.5 V) before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Data input to latch 2; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 2 that follows the complement of 2D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 3 that follows the complement of 3D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Data input to latch 3; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Data input to latch 4; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 4 that follows the complement of 4D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference; the datasheet requires all unused inputs to be held at VCC or GND for proper operation."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch enable: when high the Q outputs follow the complement of D, and when taken low the outputs latch; the minimum LE high pulse width is 6 ns for SN74ACT533."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 5 that follows the complement of 5D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Data input to latch 5; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Data input to latch 6; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 6 that follows the complement of 6D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 7 that follows the complement of 7D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Data input to latch 7; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Data input to latch 8; it must be set up at least 4 ns before LE falls and held at least 2.5 ns after LE falls."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "tri_state",+ "description": "Inverting 3-state output of latch 8 that follows the complement of 8D while LE is high and is high-impedance when OE is high."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; the recommended operating range is 4.5 V to 5.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout comes from the TOP VIEW figure on page 1, which is shown for the DB, DW, N, NS and PW pac"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0687,+ "at": "2026-10-08T16:49:55"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74act533.pdf",+ "pages": 11,+ "sha256": "3b8982b6e118ce9b",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74act533pwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74act533pwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b35b7af7fab2aea10b42335c820f1be9147e5a5c09118eef0e66af19b5b116f0",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}