component
SN74ACT374NSR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# SN74ACT374NSR++**Texas Instruments** · Flip Flops · SOP-20-208mil++SN74ACT374NSR from Texas Instruments, in a SOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Output enable input; assert low to enable outputs, high to place in high-impedance state |+| 2 | 1Q | output | Data output 1; follows 1D on positive CLK edge when OE is low, high-impedance when OE is high |+| 3 | 1D | input | Data input 1; level latched into flip-flop on positive CLK edge |+| 4 | 2D | input | Data input 2; level latched into flip-flop on positive CLK edge |+| 5 | 2Q | output | Data output 2; follows 2D on positive CLK edge when OE is low, high-impedance when OE is high |+| 6 | 3Q | output | Data output 3; follows 3D on positive CLK edge when OE is low, high-impedance when OE is high |+| 7 | 3D | input | Data input 3; level latched into flip-flop on positive CLK edge |+| 8 | 4D | input | Data input 4; level latched into flip-flop on positive CLK edge |+| 9 | 4Q | output | Data output 4; follows 4D on positive CLK edge when OE is low, high-impedance when OE is high |+| 10 | GND | power_in | Ground reference |+| 11 | CLK | input | Clock input; positive edge triggered with 70-90 MHz maximum frequency and 5 ns minimum pulse width |+| 12 | 5Q | output | Data output 5; follows 5D on positive CLK edge when OE is low, high-impedance when OE is high |+| 13 | 5D | input | Data input 5; level latched into flip-flop on positive CLK edge |+| 14 | 6D | input | Data input 6; level latched into flip-flop on positive CLK edge |+| 15 | 6Q | output | Data output 6; follows 6D on positive CLK edge when OE is low, high-impedance when OE is high |+| 16 | 7Q | output | Data output 7; follows 7D on positive CLK edge when OE is low, high-impedance when OE is high |+| 17 | 7D | input | Data input 7; level latched into flip-flop on positive CLK edge |+| 18 | 8D | input | Data input 8; level latched into flip-flop on positive CLK edge |+| 19 | 8Q | output | Data output 8; follows 8D on positive CLK edge when OE is low, high-impedance when OE is high |+| 20 | VCC | power_in | Positive supply voltage with range 4.5 V to 5.5 V |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOP-20-208mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74ACT374NSR`+- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`+- 3D model: SOP-20-208mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `sn74act374nsr-etched.step` / `sn74act374nsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74act374nsr.step` / `sn74act374nsr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74act374) (32 pp, sha256 `ccf02e6a06e5573c`, retrieved 2026-10-02, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74act374nsr-datasheet.pdf)
page.jsonadded+230@@ -0,0 +1,230 @@+{+ "slug": "sn74act374nsr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, SOP-20-208mil. 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assert low to enable outputs, high to place in high-impedance state"+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "output",+ "description": "Data output 1; follows 1D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "Data input 1; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "Data input 2; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "output",+ "description": "Data output 2; follows 2D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "output",+ "description": "Data output 3; follows 3D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "Data input 3; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "Data input 4; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "output",+ "description": "Data output 4; follows 4D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference"+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; positive edge triggered with 70-90 MHz maximum frequency and 5 ns minimum pulse width"+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "output",+ "description": "Data output 5; follows 5D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "Data input 5; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "Data input 6; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "output",+ "description": "Data output 6; follows 6D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "output",+ "description": "Data output 7; follows 7D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "Data input 7; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "Data input 8; level latched into flip-flop on positive CLK edge"+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "output",+ "description": "Data output 8; follows 8D on positive CLK edge when OE is low, high-impedance when OE is high"+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage with range 4.5 V to 5.5 V"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 32,+ "cost_usd": 0.1603,+ "at": "2026-10-02T00:54:23"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74act374",+ "pages": 32,+ "sha256": "ccf02e6a06e5573c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}