component
SN7438DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN7438DR++**Texas Instruments** · Logic Gates · SOIC-14++SN7438DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Gate 1 input A; output 1Y is low only when both 1A and 1B are high. |+| 2 | 1B | input | Gate 1 input B of the 2-input NAND buffer. |+| 3 | 1Y | output | Gate 1 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V. |+| 4 | 2A | input | Gate 2 input A of the 2-input NAND buffer. |+| 5 | 2B | input | Gate 2 input B of the 2-input NAND buffer. |+| 6 | 2Y | output | Gate 2 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V. |+| 7 | GND | power_in | Ground; voltage values are specified with respect to this network ground terminal. |+| 8 | 3Y | output | Gate 3 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V. |+| 9 | 3A | input | Gate 3 input A of the 2-input NAND buffer. |+| 10 | 3B | input | Gate 3 input B of the 2-input NAND buffer. |+| 11 | 4Y | output | Gate 4 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V. |+| 12 | 4A | input | Gate 4 input A of the 2-input NAND buffer. |+| 13 | 4B | input | Gate 4 input B of the 2-input NAND buffer. |+| 14 | VCC | power_in | Supply voltage; absolute maximum 7 V with respect to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN7438DR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn7438dr-etched.step` / `sn7438dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn7438dr.step` / `sn7438dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn7438.pdf) (27 pp, sha256 `d9f437af1d36e429`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn7438dr-datasheet.pdf)
page.jsonadded+237@@ -0,0 +1,237 @@+{+ "slug": "sn7438dr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn7438dr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn7438dr.kicad_sym",+ "sn7438dr.kicad_mod",+ "sn7438dr.glb",+ "sn7438dr.step",+ "sn7438dr.lbr",+ "docs/hero.png",+ "docs/sn7438dr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn7438dr-hero.glb",+ "sn7438dr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN7438DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn7438.pdf",+ "parts": {+ "symbol": "sn7438dr.kicad_sym",+ "footprint": "sn7438dr.kicad_mod",+ "model_3d": "sn7438dr-hero.glb",+ "model_3d_plain": "sn7438dr.glb",+ "model_3d_step": "sn7438dr-etched.step",+ "model_3d_step_plain": "sn7438dr.step",+ "lbr": "sn7438dr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2866939",+ "digikey": "296-28597-2-ND",+ "mouser": "595-SN7438DR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:43:44Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-28597-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN7438DR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Gate 1 input A; output 1Y is low only when both 1A and 1B are high."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Gate 1 input B of the 2-input NAND buffer."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Gate 1 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V."+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Gate 2 input A of the 2-input NAND buffer."+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Gate 2 input B of the 2-input NAND buffer."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Gate 2 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; voltage values are specified with respect to this network ground terminal."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Gate 3 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Gate 3 input A of the 2-input NAND buffer."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Gate 3 input B of the 2-input NAND buffer."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Gate 4 open-collector output, requires an external pull-up resistor; absolute maximum off-state output voltage 7 V."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Gate 4 input A of the 2-input NAND buffer."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Gate 4 input B of the 2-input NAND buffer."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; absolute maximum 7 V with respect to GND."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout heading on page 1 lists the SN7438 under the N package only, and lists the D package only; The Y outputs are open-collector. The allowed pin types have no open-collector class, so I used 'out",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 27,+ "cost_usd": 0.5342,+ "at": "2026-10-08T16:43:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn7438.pdf",+ "pages": 27,+ "sha256": "d9f437af1d36e429",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn7438dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn7438dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "249b514f20eb6e663adf2b777262f7bab0c01f3a107689fd4e5206e11061c270",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}