component
SN65LVDS315RGER
Public Made by Adomby adom
Texas Instruments Serializers, Deserializers, VQFN-24-EP(4x4). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+222−8@@ -1,13 +1,232 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn65lvds315rger",+ "title": "SN65LVDS315RGER",+ "brief": "Texas Instruments Serializers, Deserializers, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Serializers, Deserializers, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "interface", "sn65lvds315rger" ],+ "component": {+ "mpn": "SN65LVDS315RGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 24,+ "category": "Interface",+ "subcategory": "Serializers, Deserializers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn65lvds315",+ "parts": {+ "symbol": "sn65lvds315rger.kicad_sym",+ "footprint": "sn65lvds315rger.kicad_mod",+ "model_3d": "sn65lvds315rger.glb",+ "model_3d_step": "sn65lvds315rger.step",+ "lbr": "sn65lvds315rger.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "GNDD",+ "type": "power_in",+ "description": "Digital supply ground for VDDIO and VDDD. Tie to common ground plane."+ },+ {+ "number": "2",+ "name": "DOUT+",+ "type": "output",+ "description": "SubLVDS data link CSI-1 compliant positive output. Active during normal operation; high-impedance during power down or standby. DOUT is valid on the rising edge of CLK+."+ },+ {+ "number": "3",+ "name": "DOUT-",+ "type": "output",+ "description": "SubLVDS data link CSI-1 compliant negative output. Active during normal operation; high-impedance during power down or standby."+ },+ {+ "number": "4",+ "name": "CLK+",+ "type": "output",+ "description": "SubLVDS clock output positive (CSI-1 Mode 0 compliant). Serial clock accompanying DOUT differential data."+ },+ {+ "number": "5",+ "name": "CLK-",+ "type": "output",+ "description": "SubLVDS clock output negative (CSI-1 Mode 0 compliant)."+ },+ {+ "number": "6",+ "name": "GNDA",+ "type": "power_in",+ "description": "PLL and SubLVDS analog ground. Tie to common ground plane."+ },+ {+ "number": "7",+ "name": "TXEN",+ "type": "input",+ "description": "Transmitter enable. TXEN=1 enables the SubLVDS drivers and PLL; TXEN=0 disables them (shutdown mode). Incorporates glitch-suppression logic requiring the input to be held >10 \u00b5s to register. Do not leave floating. Referenced to VDDIO (1.8-3.3 V)."+ },+ {+ "number": "8",+ "name": "MODE",+ "type": "input",+ "description": "MODE selects line-counting behavior for EOF signalling when VS and HS do not reset during the same DCLK cycle (0 = line counter disabled; 1 = counter enabled). TI recommends MODE=high when unsure. Do not leave floating."+ },+ {+ "number": "9",+ "name": "VDDA",+ "type": "power_in",+ "description": "PLL and SubLVDS I/O analog supply (1.8 V only). Bypass locally to GNDA."+ },+ {+ "number": "10",+ "name": "D0",+ "type": "input",+ "description": "Parallel pixel data input bit 0 (LSB). Sampled on the falling DCLK edge; latched into the device on that edge. CMOS input with bus hold, referenced to VDDIO (1.65-3.6 V range)."+ },+ {+ "number": "11",+ "name": "D1",+ "type": "input",+ "description": "Parallel pixel data input bit 1. Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "12",+ "name": "D2",+ "type": "input",+ "description": "Parallel pixel data input bit 2. Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "13",+ "name": "D3",+ "type": "input",+ "description": "Parallel pixel data input bit 3. Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "14",+ "name": "D4",+ "type": "input",+ "description": "Parallel pixel data input bit 4. Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "15",+ "name": "D5",+ "type": "input",+ "description": "Parallel pixel data input bit 5. Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "16",+ "name": "DCLK",+ "type": "input",+ "description": "Data input clock; represents the camera pixel clock. All 8 pixel bits, VS and HS are latched on the falling edge of DCLK. Supports 3.5-13 MHz (FSEL=0) or 7-27 MHz (FSEL=1). CMOS input with bus hold."+ },+ {+ "number": "17",+ "name": "GNDD",+ "type": "power_in",+ "description": "Digital supply ground for VDDIO and VDDD. Second GNDD pin; tie to ground plane."+ },+ {+ "number": "18",+ "name": "D6",+ "type": "input",+ "description": "Parallel pixel data input bit 6. Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "19",+ "name": "D7",+ "type": "input",+ "description": "Parallel pixel data input bit 7 (MSB). Sampled on the falling DCLK edge. CMOS input with bus hold."+ },+ {+ "number": "20",+ "name": "VS",+ "type": "input",+ "description": "Vertical Sync (also called frame sync). High-active data input sampled on every falling DCLK edge. CMOS input with bus hold, referenced to VDDIO."+ },+ {+ "number": "21",+ "name": "HS",+ "type": "input",+ "description": "Horizontal Sync (also called line sync). High-active data input sampled on every falling DCLK edge. CMOS input with bus hold, referenced to VDDIO."+ },+ {+ "number": "22",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O supply voltage for the CMOS inputs D[0:7], HS, VS and DCLK. Supports 1.8 V to 3.3 V to match the host/camera GPIO rail."+ },+ {+ "number": "23",+ "name": "VDDD",+ "type": "power_in",+ "description": "Digital core supply voltage (1.8 V only). Bypass locally to GNDD."+ },+ {+ "number": "24",+ "name": "FSEL",+ "type": "input",+ "description": "Frequency Select. FSEL=0 selects DCLK range 3.5-13 MHz; FSEL=1 selects DCLK range 7-27 MHz. Do not leave floating."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn65lvds315",+ "pages": 43,+ "sha256": "c6311404a0aac6c9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "VQFN-24-EP(4x4)",+ "Category": "Interface",+ "Pins": "24"+ }+ },+ "variants": [+ {+ "mpn": "SN65LVDS315RGER",+ "kind": "packaging"+ },+ {+ "mpn": "SN65LVDS315RGERRGET",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn65lvds315rger"+ ],+ "discovery_pitch": "SN65LVDS315RGER (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +244,5 @@ "docs/sn65lvds315rger-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }