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SN65LV1224BMDBREP
Public Made by Adomby adom
Texas Instruments Serializers, Deserializers, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+64@@ -0,0 +1,64 @@+# SN65LV1224BMDBREP++**Texas Instruments** · Serializers, Deserializers · SSOP-28-208mil++SN65LV1224BMDBREP from Texas Instruments, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog circuit ground for the PLL and analog circuits. |+| 2 | RCLK_R/F | input | LVTTL logic input; low selects an RCLK falling-edge data strobe and high selects an RCLK rising-edge data strobe. |+| 3 | REFCLK | input | LVTTL logic input that supplies the reference clock for the internal PLL frequency; a local clock must be applied to this pin for the deserializer PLL to initialize. |+| 4 | AVCC | power_in | Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V. |+| 5 | RI+ | input | Noninverting LVDS differential serial data input. |+| 6 | RI- | input | Inverting LVDS differential serial data input. |+| 7 | PWRDN | input | LVTTL logic input; asserting it low turns off the PLL and places the outputs into high-impedance for low-power mode, and it must be held low for a minimum of 16 ns to initiate power down. |+| 8 | REN | input | LVTTL logic input; driving it low places ROUT0-ROUT9 and RCLK into the high-impedance state. |+| 9 | RCLK | output | LVTTL-level recovered clock output used to strobe ROUTx; it is 3-stated when REN is low or LOCK is high. |+| 10 | LOCK | output | LVTTL-level output that goes low when the deserializer PLL locks onto the embedded clock edge; ROUT data is valid only while LOCK is low. |+| 11 | AVCC | power_in | Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V. |+| 12 | AGND | power_in | Analog circuit ground for the PLL and analog circuits. |+| 13 | AGND | power_in | Analog circuit ground for the PLL and analog circuits. |+| 14 | DGND | power_in | Digital circuit ground. |+| 15 | ROUT9 | tri_state | LVTTL parallel data output bit 9, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 16 | ROUT8 | tri_state | LVTTL parallel data output bit 8, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 17 | ROUT7 | tri_state | LVTTL parallel data output bit 7, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 18 | ROUT6 | tri_state | LVTTL parallel data output bit 6, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 19 | ROUT5 | tri_state | LVTTL parallel data output bit 5, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 20 | DGND | power_in | Digital circuit ground. |+| 21 | DVCC | power_in | Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V. |+| 22 | DGND | power_in | Digital circuit ground. |+| 23 | DVCC | power_in | Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V. |+| 24 | ROUT4 | tri_state | LVTTL parallel data output bit 4, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 25 | ROUT3 | tri_state | LVTTL parallel data output bit 3, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 26 | ROUT2 | tri_state | LVTTL parallel data output bit 2, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 27 | ROUT1 | tri_state | LVTTL parallel data output bit 1, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |+| 28 | ROUT0 | tri_state | LVTTL parallel data output bit 0, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SSOP-28-208mil |+| Category | Interface |+| Pins | 28 |++## CAD (KiCad official)++- Symbol: `SN65LV1224BMDBREP`+- Footprint: `Package_SO:SSOP-28_5.3x10.2mm_P0.65mm`+- 3D model: SSOP-28-208mil (KiCad packages3D, STEP)+- 3D model files: `sn65lv1224bmdbrep-etched.step` / `sn65lv1224bmdbrep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lv1224bmdbrep.step` / `sn65lv1224bmdbrep.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn65lv1023a-ep) (29 pp, sha256 `2c0fadd4093ca5b1`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lv1224bmdbrep-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "sn65lv1224bmdbrep",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn65lv1224bmdbrep.kicad_sym",+ "sn65lv1224bmdbrep.kicad_mod",+ "sn65lv1224bmdbrep.glb",+ "sn65lv1224bmdbrep.step",+ "sn65lv1224bmdbrep.lbr",+ "docs/hero.png",+ "docs/sn65lv1224bmdbrep-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn65lv1224bmdbrep-hero.glb",+ "sn65lv1224bmdbrep-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN65LV1224BMDBREP",+ "manufacturer": "Texas Instruments",+ "package": "SSOP-28-208mil",+ "pin_count": 28,+ "category": "Interface",+ "subcategory": "Serializers, Deserializers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn65lv1023a-ep",+ "parts": {+ "symbol": "sn65lv1224bmdbrep.kicad_sym",+ "footprint": "sn65lv1224bmdbrep.kicad_mod",+ "model_3d": "sn65lv1224bmdbrep-hero.glb",+ "model_3d_plain": "sn65lv1224bmdbrep.glb",+ "model_3d_step": "sn65lv1224bmdbrep-etched.step",+ "model_3d_step_plain": "sn65lv1224bmdbrep.step",+ "lbr": "sn65lv1224bmdbrep.lbr"+ },+ "distributor_links": {+ "lcsc": "C2877454",+ "digikey": "296-21244-2-ND",+ "mouser": "595-65LV1224BMDBREP"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:21:38Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-21244-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-65LV1224BMDBREP",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog circuit ground for the PLL and analog circuits."+ },+ {+ "number": "2",+ "name": "RCLK_R/F",+ "type": "input",+ "description": "LVTTL logic input; low selects an RCLK falling-edge data strobe and high selects an RCLK rising-edge data strobe."+ },+ {+ "number": "3",+ "name": "REFCLK",+ "type": "input",+ "description": "LVTTL logic input that supplies the reference clock for the internal PLL frequency; a local clock must be applied to this pin for the deserializer PLL to initialize."+ },+ {+ "number": "4",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V."+ },+ {+ "number": "5",+ "name": "RI+",+ "type": "input",+ "description": "Noninverting LVDS differential serial data input."+ },+ {+ "number": "6",+ "name": "RI-",+ "type": "input",+ "description": "Inverting LVDS differential serial data input."+ },+ {+ "number": "7",+ "name": "PWRDN",+ "type": "input",+ "description": "LVTTL logic input; asserting it low turns off the PLL and places the outputs into high-impedance for low-power mode, and it must be held low for a minimum of 16 ns to initiate power down."+ },+ {+ "number": "8",+ "name": "REN",+ "type": "input",+ "description": "LVTTL logic input; driving it low places ROUT0-ROUT9 and RCLK into the high-impedance state."+ },+ {+ "number": "9",+ "name": "RCLK",+ "type": "output",+ "description": "LVTTL-level recovered clock output used to strobe ROUTx; it is 3-stated when REN is low or LOCK is high."+ },+ {+ "number": "10",+ "name": "LOCK",+ "type": "output",+ "description": "LVTTL-level output that goes low when the deserializer PLL locks onto the embedded clock edge; ROUT data is valid only while LOCK is low."+ },+ {+ "number": "11",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V."+ },+ {+ "number": "12",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog circuit ground for the PLL and analog circuits."+ },+ {+ "number": "13",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog circuit ground for the PLL and analog circuits."+ },+ {+ "number": "14",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital circuit ground."+ },+ {+ "number": "15",+ "name": "ROUT9",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 9, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "16",+ "name": "ROUT8",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 8, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "17",+ "name": "ROUT7",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 7, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "18",+ "name": "ROUT6",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 6, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "19",+ "name": "ROUT5",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 5, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "20",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital circuit ground."+ },+ {+ "number": "21",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V."+ },+ {+ "number": "22",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital circuit ground."+ },+ {+ "number": "23",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V."+ },+ {+ "number": "24",+ "name": "ROUT4",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 4, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "25",+ "name": "ROUT3",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 3, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "26",+ "name": "ROUT2",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 2, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "27",+ "name": "ROUT1",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 1, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ },+ {+ "number": "28",+ "name": "ROUT0",+ "type": "tri_state",+ "description": "LVTTL parallel data output bit 0, valid when LOCK is low and strobed by RCLK; 3-stated when REN is low."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The MPN SN65LV1224BMDBREP is the SN65LV1224B deserializer in the 28-pin SSOP (DB) package, per the o; The terminal table gives ROUT0–ROUT9 as pins '28–24, 19–15' without a per-pin mapping. The mapping a; Pins 12 and 13 are both AGND, and pins 4 and 11 are both AVCC. Pins 14, 20 and 22 are DGND, and pins",+ "8/28 pins cited to the wrong page (name found elsewhere): ['16:ROUT8@p7', '17:ROUT7@p7', '18:ROUT6@p7', '19:ROUT5@p7']"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0802,+ "at": "2026-10-08T20:20:46"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn65lv1023a-ep",+ "pages": 29,+ "sha256": "2c0fadd4093ca5b1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 28,+ "described": 28,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn65lv1224bmdbrep.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.8,+ 10.2,+ 2.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7aa76979ae41da44bded1ed74115012868f2f3f5a757faf32bb9df4f92c1e313",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn65lv1224bmdbrep-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.8,+ 10.2,+ 2.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "73f8ecaef18761927577fcca49cfc6d50735ab88cb10462f22737f10e0ce1e1c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}