SM74HC595D

@@ -0,0 +1,55 @@+# SM74HC595D++**Shenzhen Sunmoon Micro** · Shifting Register · SOP-16++SM74HC595D from Shenzhen Sunmoon Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q1 | tri_state | Parallel latched output bit 1 from the storage register. Three-state; enabled when /G (pin 13) is low. |+| 2 | Q2 | tri_state | Parallel latched output bit 2. Three-state, enabled by /G low. |+| 3 | Q3 | tri_state | Parallel latched output bit 3. Three-state, enabled by /G low. |+| 4 | Q4 | tri_state | Parallel latched output bit 4. Three-state, enabled by /G low. |+| 5 | Q5 | tri_state | Parallel latched output bit 5. Three-state, enabled by /G low. |+| 6 | Q6 | tri_state | Parallel latched output bit 6. Three-state, enabled by /G low. |+| 7 | Q7 | tri_state | Parallel latched output bit 7 (MSB of the 8-bit output). Three-state, enabled by /G low. |+| 8 | GND | power_in | Logic ground reference (0 V). |+| 9 | Q7' | output | Serial data output from the last stage of the shift register. Used to daisy-chain multiple 74HC595 devices; not three-state. |+| 10 | /SCLR | input | Active-low asynchronous shift-register clear. Driving low forces all shift-register bits to 0 (Q7' = 0); does not affect the storage latch until an RCK edge. |+| 11 | SCK | input | Shift-register clock. Data on SER is shifted into the shift register on the rising edge. Max 50 MHz (typ. 52 MHz at Vcc = 4.5 V). |+| 12 | RCK | input | Storage/latch register clock. On the rising edge, the shift-register contents are transferred to the output storage register (latched to Q0-Q7). |+| 13 | /G | input | Active-low output enable for the parallel outputs Q0-Q7. Low enables the latched data onto the outputs; high places Q0-Q7 in high-impedance (3-state). |+| 14 | SER | input | Serial data input to the shift register. Sampled on the rising edge of SCK; tSU ≈ 16 ns, tH ≈ 3 ns. |+| 15 | Q0 | tri_state | Parallel latched output bit 0 (LSB of the 8-bit output). Three-state, enabled by /G low. |+| 16 | VCC | power_in | Positive supply voltage, 2.0 V to 6.0 V. Bypass with 100 nF near the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Shenzhen Sunmoon Micro |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `SM74HC595DD`++## CAD (KiCad official)++- Symbol: `SM74HC595D`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Shenzhen Sunmoon Micro datasheet](docs/sm74hc595d-datasheet.pdf) (7 pp, sha256 `a82a24e37bce2202`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sm74hc595d-datasheet.pdf)

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